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Jacob Savir
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2000 – 2009
- 2006
- [j48]Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara:
Effect of BIST Pretest on IC Defect Level. IEICE Trans. Inf. Syst. 89-D(10): 2626-2636 (2006) - [j47]Zhen Guo, Jacob Savir:
Coefficient-based test of parametric faults in analog circuits. IEEE Trans. Instrum. Meas. 55(1): 150-157 (2006) - [c40]Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara:
BIST Pretest of ICs: Risks and Benefits. VTS 2006: 142-149 - 2005
- [j46]Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara:
Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST. IEICE Trans. Inf. Syst. 88-D(6): 1210-1216 (2005) - [j45]Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara:
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths. IEICE Trans. Inf. Syst. 88-D(8): 1940-1947 (2005) - [j44]Jacob Savir:
Built-in online and offline test of airborne digital systems. IEEE Trans. Instrum. Meas. 54(3): 965-974 (2005) - 2004
- [j43]Amit M. Sheth, Jacob Savir:
Scan Latch Design for Test Applications. J. Electron. Test. 20(2): 213-216 (2004) - [j42]Zhen Guo, Jacob Savir:
Analog Circuit Test Using Transfer Function Coefficient Estimates. IEICE Trans. Inf. Syst. 87-D(3): 642-646 (2004) - [c39]Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara:
Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. Asian Test Symposium 2004: 32-39 - 2003
- [j41]Jacob Savir, Zhen Guo:
Test limitations of parametric faults in analog circuits. IEEE Trans. Instrum. Meas. 52(5): 1444-1454 (2003) - [j40]Amit M. Sheth, Jacob Savir:
Single-clock, single-latch, scan design. IEEE Trans. Instrum. Meas. 52(5): 1455-1457 (2003) - [c38]Zhen Guo, Jacob Savir:
Analog Circuit Test using Transfer Function Coe .cient Estimates. ITC 2003: 1155-1163 - 2002
- [c37]Jacob Savir, Zhen Guo:
Test Limitations of Parametric Faults in Analog Circuits. Asian Test Symposium 2002: 39-44 - [c36]Zhen Guo, Jacob Savir:
Observer-Based Test of Analog Linear Time-Invariant Circuits. DELTA 2002: 13-17 - [c35]Jacob Savir, Zhen Guo:
On the Detectability of Parametric Faults in Analog Circuits. ICCD 2002: 273-276 - 2001
- [j39]Jacob Savir:
BIST-Based Fault Diagnosis in the Presence of Embedded Memories. VLSI Design 12(4): 487-500 (2001) - [j38]Jacob Savir:
Test Generators Need to be Modified to Handle CMOS Designs. VLSI Design 12(4): 515-525 (2001) - [j37]Jacob Savir:
BIST Analysis of an Embedded Memory Associated Logic. VLSI Design 12(4): 563-578 (2001) - [c34]Zhen Guo, Xi Min Zhang, Jacob Savir, Yun-Qing Shi:
On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks. Asian Test Symposium 2001: 338-343 - 2000
- [j36]Jacob Savir:
Distributed BIST Architecture to Combat Delay Faults. J. Electron. Test. 16(4): 369-380 (2000) - [c33]Jacob Savir:
On testing safety-sensitive digital systems. Asian Test Symposium 2000: 478-483 - [c32]Jacob Savir:
On-line and off-line test of airborne digital systems: a reliability study. ITC 2000: 35-44 - [c31]Qiang Peng, Miron Abramovici, Jacob Savir:
MUST: multiple-stem analysis for identifying sequentially untestable faults. ITC 2000: 839-846
1990 – 1999
- 1999
- [j35]Jacob Savir:
Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections. J. Electron. Test. 15(3): 279-296 (1999) - [j34]Jacob Savir:
Distributed Generation of Weighted Random Patterns. IEEE Trans. Computers 48(12): 1364-1368 (1999) - [c30]Jacob Savir:
Memory Chip BIST Architecture. Great Lakes Symposium on VLSI 1999: 384- - [c29]Jacob Savir:
Design for Testability to Combat Delay Faults. ICCD 1999: 407-411 - 1998
- [j33]Jacob Savir:
On-Chip Weighted Random Patterns. J. Electron. Test. 13(1): 41-50 (1998) - [j32]Jacob Savir:
Random Pattern Testability of Memory Control Logic. IEEE Trans. Computers 47(3): 305-312 (1998) - [j31]Jacob Savir:
Salvaging Test Windows in BIST Diagnostics. IEEE Trans. Computers 47(4): 486-491 (1998) - [j30]Jacob Savir:
Random pattern testability of memory address logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(12): 1310-1318 (1998) - [j29]Jacob Savir:
Redundancy revisited. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 620-624 (1998) - [c28]Jacob Savir:
BIST Diagnostics, Part 1: Simulation Models. Asian Test Symposium 1998: 8-14 - [c27]Jacob Savir:
Distributed Generation of Weighted Random Patterns. VTS 1998: 225-233 - 1997
- [j28]Jacob Savir:
Delay Test Generation: A Hardware Perspective. J. Electron. Test. 10(3): 245-254 (1997) - [j27]Jacob Savir:
Module Level Weighted Random Patterns. J. Electron. Test. 10(3): 283-287 (1997) - [j26]Jacob Savir:
Reduced Latch Count Shift Registers. J. Electron. Test. 11(2): 183-185 (1997) - [c26]Jacob Savir:
On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers. Asian Test Symposium 1997: 296-299 - [c25]Jacob Savir:
On Chip Weighted Random Patterns. Asian Test Symposium 1997: 343-352 - [c24]Jacob Savir:
BIST-Based Fault Diagnosis in the Presence of Embedded Memories. ICCD 1997: 37-47 - [c23]Jacob Savir:
Scan Latch Design for Delay Test. ITC 1997: 446-453 - [c22]Jacob Savir:
Random pattern testability of memory control logic. VTS 1997: 399-409 - [c21]Jacob Savir:
Salvaging test windows in BIST diagnostic. VTS 1997: 416-425 - 1996
- [j25]Jacob Savir:
Reducing the MISR Size. IEEE Trans. Computers 45(8): 930-938 (1996) - [c20]Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma:
Delay Fault Testing: How Robust are Our Models? VTS 1996: 502-503 - 1995
- [j24]Jacob Savir:
Shrinking wide compressors [BIST]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1379-1387 (1995) - [c19]Jacob Savir:
Generator choices for delay test. Asian Test Symposium 1995: 214-221 - [c18]Jacob Savir:
Module level weighted random patterns. Asian Test Symposium 1995: 274-278 - [c17]Jacob Savir:
On shrinking wide compressors. VTS 1995: 108-117 - 1994
- [j23]Jacob Savir, Srinivas Patil:
Broad-side delay test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8): 1057-1064 (1994) - [j22]Jacob Savir, Srinivas Patil:
On broad-side delay test. IEEE Trans. Very Large Scale Integr. Syst. 2(3): 368-372 (1994) - [c16]Jacob Savir, Srinivas Patil:
On broad-side delay test. VTS 1994: 284-290 - 1993
- [j21]Jacob Savir, Srinivas Patil:
Scan-based transition test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8): 1232-1241 (1993) - [j20]Jacob Savir, Paul H. Bardell:
Built-In Self-Test: Milestones and Challenges. VLSI Design 1(1): 23-44 (1993) - 1992
- [j19]Jacob Savir, Robert F. Berry:
AC strength of a pattern generator. J. Electron. Test. 3(2): 119-125 (1992) - [j18]A. Boneh, Jacob Savir:
Statistical Resistance to Detection. IEEE Trans. Computers 41(1): 123-126 (1992) - [j17]Jacob Savir, William H. McAnney:
A Multiple Seed Linear Feedback Shift Register. IEEE Trans. Computers 41(2): 250-252 (1992) - [c15]Jacob Savir:
Skewed-Load Transition Test: Part 1, Calculus. ITC 1992: 705-713 - [c14]Srinivas Patil, Jacob Savir:
Skewed-Load Transition Test: Part 2, Coverage. ITC 1992: 714-722 - [c13]Jacob Savir:
Developments in delay testing. VTS 1992: 247-253 - 1991
- [j16]Jacob Savir, William H. McAnney, Salvatore R. Vecchio:
Testing for Coupled Cells in Random-Access Memories. IEEE Trans. Computers 40(10): 1177-1180 (1991) - [j15]Jacob Savir, Paul H. Bardell:
Partitioning of polynomial tasks: test generation, an example. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(11): 1465-1468 (1991) - [c12]Jacob Savir, Robert F. Berry:
At-Speed Test is not Necessarily an AC Test. ITC 1991: 722-728 - 1990
- [c11]Jacob Savir, William H. McAnney:
A multiple seed linear feedback shift register. ITC 1990: 657-659 - [c10]Jacob Savir:
AC product defect level and yield loss. ITC 1990: 726-738
1980 – 1989
- 1989
- [c9]Jacob Savir, William H. McAnney, Salvatore R. Vecchio:
Testing for Coupled Cells in Random-Access Memories. ITC 1989: 439-451 - 1988
- [j14]Jacob Savir, William H. McAnney:
Random Pattern Testability of Delay Faults. IEEE Trans. Computers 37(3): 291-300 (1988) - [j13]William H. McAnney, Jacob Savir:
Built-In Checking of the Correct Self-Test Signature. IEEE Trans. Computers 37(9): 1142-1145 (1988) - [c8]Jacob Savir:
Why Partial Design Verification Works Better Than It Should. DAC 1988: 704-707 - [c7]Jacob Savir, William H. McAnney:
Identification of Failing Tests with Cycling Registers. ITC 1988: 322-328 - 1987
- [j12]Jacob Savir, William H. McAnney, Salvatore R. Vecchio:
Fault Propagation Through Embedded Multiport Memories. IEEE Trans. Computers 36(5): 592-602 (1987) - 1986
- [j11]Jacob Savir:
The Bidirectional Double Latch (BDDL). IEEE Trans. Computers 35(1): 65-66 (1986) - [c6]William H. McAnney, Jacob Savir:
Built-In Checking of the Correct Self-Test Signature. ITC 1986: 54-59 - [c5]Jacob Savir, William H. McAnney:
Random Pattern Testability of Delay Faults. ITC 1986: 263-273 - 1985
- [j10]Thomas H. Spencer, Jacob Savir:
Layout Influences Testability. IEEE Trans. Computers 34(3): 287-290 (1985) - [c4]Jacob Savir, William H. McAnney, Salvatore R. Vecchio:
Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory. ITC 1985: 100-105 - [c3]Jacob Savir, William H. McAnney, Salvatore R. Vecchio:
Random Pattern Testing for Address-Line Faults in an Embedded Multiport Memory. ITC 1985: 106-114 - 1984
- [j9]Jacob Savir, Gary S. Ditlow, Paul H. Bardell:
Random Pattern Testability. IEEE Trans. Computers 33(1): 79-90 (1984) - [j8]Jacob Savir, Paul H. Bardell:
On Random Pattern Test Length. IEEE Trans. Computers 33(6): 467-474 (1984) - 1983
- [j7]Jacob Savir:
A New Empirical Test for the Quality of Random Integer Generators. IEEE Trans. Computers 32(10): 960-961 (1983) - [j6]Jacob Savir:
Good Controllability and Observability Do Not Guarantee Good Testability. IEEE Trans. Computers 32(12): 1198-1200 (1983) - [c2]Jacob Savir, Paul H. Bardell:
On Random Pattern Test Length. ITC 1983: 95-107 - 1981
- [j5]Jacob Savir:
Syndrome-Testing of "Syndrome-Untestable" Combinational Circuits. IEEE Trans. Computers 30(8): 606-608 (1981) - [j4]Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith:
The Weighted Syndrome Sums Approach to VLSI Testing. IEEE Trans. Computers 30(12): 996-1000 (1981) - [c1]Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith:
VLSI Self-Testing Based on Syndrome Techniques. ITC 1981: 102-109 - 1980
- [j3]Jacob Savir:
Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection. IEEE Trans. Computers 29(5): 410-416 (1980) - [j2]Jacob Savir:
Syndrome-Testable Design of Combinational Circuits. IEEE Trans. Computers 29(6): 442-451 (1980) - [j1]Jacob Savir:
Detection of Single Intermittent Faults in Sequential Circuits. IEEE Trans. Computers 29(7): 673-678 (1980)
Coauthor Index
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