research-article

Throughput-driven synthesis of embedded software for pipelined execution on multicore architectures

Authors:

Soheil GhiasiAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 8, Issue 2

Article No.: 11, Pages 1 - 35

https://doi.org/10.1145/1457255.1457258

Published: 09 February 2009 Publication History

Abstract

We present a methodology for pipelined software synthesis of streaming applications. First, we develop a versatile task assignment algorithm capable of optimizing realistically-arbitrary cost functions for two cores. The algorithm is exact (i.e., theoretically optimal) contrary to existing heuristics. Second, our approximation technique provides an adjustable knob to trade solution quality with algorithm runtime and memory. Third, we develop a recursive heuristic for more cores. FPGA-based emulated experiments validate our theoretical results. The exact algorithm yields 1.7 × throughput improvement. The approximation method offers a range of tradeoff points (e.g., 3 × faster with 20 × less memory) while degrading the throughput only 1% to 5%.

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Cited By

Hashemi MBarijough KGhiasi S(2016)Throughput-Driven Parallel Embedded Software Synthesis from Synchronous Dataflow Models: Caveats and RemediesModel-Implementation Fidelity in Cyber Physical System Design10.1007/978-3-319-47307-9_4(91-127)Online publication date: 10-Dec-2016
https://doi.org/10.1007/978-3-319-47307-9_4
Aleti ABuhnova BGrunske LKoziolek AMeedeniya I(2013)Software Architecture Optimization MethodsIEEE Transactions on Software Engineering10.1109/TSE.2012.6439:5(658-683)Online publication date: 1-May-2013
https://dl.acm.org/doi/10.1109/TSE.2012.64
Javaid HWitono DParameswaran S(2013)Multi-mode pipelined MPSoCs for streaming applications2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2013.6509601(231-236)Online publication date: Jan-2013
https://doi.org/10.1109/ASPDAC.2013.6509601
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Index Terms

Throughput-driven synthesis of embedded software for pipelined execution on multicore architectures
1. Hardware
  1. Hardware validation
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 8, Issue 2

January 2009

243 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/1457255

Issue’s Table of Contents

Copyright © 2009 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 09 February 2009

Accepted: 01 August 2008

Revised: 01 March 2008

Received: 01 August 2007

Published in TECS Volume 8, Issue 2

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Cited By

Hashemi MBarijough KGhiasi S(2016)Throughput-Driven Parallel Embedded Software Synthesis from Synchronous Dataflow Models: Caveats and RemediesModel-Implementation Fidelity in Cyber Physical System Design10.1007/978-3-319-47307-9_4(91-127)Online publication date: 10-Dec-2016
https://doi.org/10.1007/978-3-319-47307-9_4
Aleti ABuhnova BGrunske LKoziolek AMeedeniya I(2013)Software Architecture Optimization MethodsIEEE Transactions on Software Engineering10.1109/TSE.2012.6439:5(658-683)Online publication date: 1-May-2013
https://dl.acm.org/doi/10.1109/TSE.2012.64
Javaid HWitono DParameswaran S(2013)Multi-mode pipelined MPSoCs for streaming applications2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2013.6509601(231-236)Online publication date: Jan-2013
https://doi.org/10.1109/ASPDAC.2013.6509601
Javaid HParameswaran SJavaid HParameswaran S(2013)Multi-mode Pipelined MPSoCsPipelined Multiprocessor System-on-Chip for Multimedia10.1007/978-3-319-01113-4_8(147-162)Online publication date: 26-Nov-2013
https://doi.org/10.1007/978-3-319-01113-4_8
Javaid HParameswaran SJavaid HParameswaran S(2013)Optimisation FrameworkPipelined Multiprocessor System-on-Chip for Multimedia10.1007/978-3-319-01113-4_3(53-64)Online publication date: 26-Nov-2013
https://doi.org/10.1007/978-3-319-01113-4_3
Javaid HParameswaran SJavaid HParameswaran S(2013)Literature SurveyPipelined Multiprocessor System-on-Chip for Multimedia10.1007/978-3-319-01113-4_2(21-52)Online publication date: 26-Nov-2013
https://doi.org/10.1007/978-3-319-01113-4_2
Javaid HParameswaran SJavaid HParameswaran S(2013)IntroductionPipelined Multiprocessor System-on-Chip for Multimedia10.1007/978-3-319-01113-4_1(1-20)Online publication date: 26-Nov-2013
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Mosavi M(2010)Use of Accurate GPS Timing Based on Radial Basis Probabilistic Neural Network in Electric SystemsProceedings of the 2010 International Conference on Electrical and Control Engineering10.1109/iCECE.2010.1483(2572-2575)Online publication date: 25-Jun-2010
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Hashemi MGhiasi S(2010)Versatile task assignment for heterogeneous soft dual-processor platformsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.204185629:3(414-425)Online publication date: 1-Mar-2010
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Yi Wei Pan Hongbing Pan Peng Li Li Gao Minglun Hou Ning Du Gaoming Zhang Duoli (2010)Application-level pipelining on Hierarchical NoCProceedings of 2010 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2010.5537706(3873-3876)Online publication date: May-2010
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