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Performance Evaluation of Congestion-Aware Routing with DVFS on a Millimeter-Wave Small-World Wireless NoC

Published: 18 November 2014 Publication History

Abstract

The mm-wave small-world wireless NoC (mSWNoC) has emerged as an enabling interconnection infrastructure for designing high-bandwidth and energy-efficient multicore chips. In this mSWNoC architecture, long-range communication predominately takes place through the wireless shortcuts operating in the range of 10--100GHz, whereas short-range data exchange occurs through conventional metal wires. This results in performance advantages (lower latency and energy dissipation), mainly stemming from using the wireless links as long-range shortcuts between far-apart cores. The performance gain introduced by the wireless channels can be enhanced further if the wireline links of the mSWNoC are optimized according to the traffic patterns arising out of the application workloads. While there is significant energy savings, and hence temperature reduction, in the network due to the mSWNoC architecture, a load-imbalanced network is still susceptible to local temperature hotspots. In this work, we demonstrate that by incorporating congestion-avoidance routing with network-level dynamic voltage and frequency scaling (DVFS) in an mSWNoC, the power and thermal profiles can be improved without a significant impact on the overall network performance. In this work, we demonstrate how novel interconnect architectures enabled by the on-chip wireless links coupled with power management strategies can improve the energy and thermal characteristics of an mSWNoC significantly without introducing any performance degradation with respect to the conventional mesh-based NoC.

References

[1]
C. Bienia. 2011. Benchmarking modern multiprocessors. Ph.D. Dissertation, Princeton University, Princeton, NJ.
[2]
N. Binkert, B. Beckmann, G. Black, S. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. Hill, and D. Wood. 2011. The GEM5 simulator. ACM SIGARCH Comput. Archit. News. 39, 2, 1--7.
[3]
P. Bogdan, R. Marculescu, and S. Jain. 2013. Dynamic power management for multidomain system-on-chip platforms: An optimal control approach. ACM Trans. Des. Autom. Electron. Syst. 18, 4, Article 46.
[4]
K. Chang, S. Deb, A. Ganguly, X. Yu, S. P. Sah, P. P. Pande, B. Belzer, and D. Heo. 2012. Performance evaluation and design trade-offs for wireless network-on-chip architectures. J. Emerg. Technol. Comput. Syst. 8, 3.
[5]
P. Chaparro, J. González, G. Magklis, Q. Cai, and A. González. 2007. Understanding the thermal implications of multicore architectures. IEEE Trans. Parallel Distrib. Syst. 18, 8, 1055--1065.
[6]
R. David, P. Bogdan, and R. Marculescu. 2012. Dynamic power management for multicores: Case study using the intel SCC. In Proceedings of the IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). 147--152.
[7]
S. Deb, A. Ganguly, P. P. Pande, B. Belzer, and D. Heo. 2012a. Wireless NoC as interconnection backbone for multicore chips: Promises and challenges. IEEE J. Emerg. Select. Topics Circuits Syst. 2, 2, 228--239.
[8]
S. Deb, K. Chang, X. Yu, S. P. Sah, M. Cosic, A. Ganguly, P. P. Pande, B. Belzer, and D. Heo. 2012b. Design of an energy efficient CMOS compatible NoC architecture with millimeter-wave wireless interconnects. IEEE Trans. Comput.
[9]
S. Deb, K. Chang, M. Cosic, A. Ganguly, P. P. Pande, D. Heo, and B. Belzer. 2012c. CMOS compatible many-core NoC architectures with multi-channel millimeter-wave wireless links. In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI'12). 165--170.
[10]
D. Di Tomaso, A. Kodi, S. Kaya, and D. Matolak. 2011. iWise: Inter-router wireless scalable express channels for network-on-chips (NoCs) Architectures. In Proceedings of the IEEE Symposium on High Performance Interconnects (HOTI'11). 11--18.
[11]
M. Ebrahimi, M. Daneshtalab, F. Farahnakian, J. Plosila, P. Liljeberg, M. Palesi, and H. Tenhunen. 2012a. HARAQ: Congestion-aware learning model for highly adaptive routing algorithm in on-chip networks. In Proceedings of the 6th IEEE/ACM International Symposium on Networks on Chip (NoCS). 19--26.
[12]
M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen. 2012b. CATRA—Congestion aware trapezoid-based routing algorithm for on-chip networks. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE). 320--325.
[13]
J. Flich, T. Skeie, A. Mejía, O. Lysne, P. López, A. Robles, J. Duato, M. Koibuchi, T. Rokicki, and J. C. Sancho. 2012. A survey and evaluation of topology-agnostic deterministic routing algorithms. IEEE Trans. Parallel Distrib. Syst. 23, 3, 405--425.
[14]
A. Ganguly, K. Chang, S. Deb, P. P. Pande, B. Belzer, and C. Teuscher. 2011a. Scalable hybrid wireless network-on-chip architectures for multi-core systems. IEEE Trans. Comput. 60, 10, 1485--1502.
[15]
A. Ganguly, P. Wettin, K. Chang, and P. P. Pande. 2011b. Complex network inspired fault-tolerant NoC architectures with wireless links. In Proceedings of the International Symposium on Networks-on-Chip (NoCS'11). 169--176.
[16]
S. Garg, D. Marculescu, and R. Marculescu. 2012. Technology-driven limits on run-time power management algorithms for multi-processor systems on chip. J. Emerg. Technol. Comput. Syst. 8, 4.
[17]
S. J. Hollis, C. Jackson, P. Bogdan, and R. Marculescu. 2014. Exploiting emergence in on-chip interconnects. IEEE Trans. Comput. 63, 3, 570--582.
[18]
H. S. Kia and C. Ababei. 2011. A new fault-tolerant and congestion-aware adaptive routing algorithm for regular networks-on-chip. IEEE Congress on Evolutionary Computation (CEC). 2465--2472.
[19]
W. Kim, M. Gupta, G.-Y. Wei, and D. Brooks. 2008. System level analysis of fast, per-core DVFS using on-chip switching regulators. In Proceedings of the International Symposium on High Performance Computer Architecture. 123--134.
[20]
A. Kumar, L.-S. Peh, P. Kundu, and N. K. Jha. 2008a. Toward ideal on-chip communication using express virtual channels. IEEE Micro. 28, 1, 80--90.
[21]
A. Kumar, L.-S. Peh, and N. K. Jha. 2008b. Token flow control. In Proceedings of the 41st IEEE/ACM International Symposium on Microarchitecture. 342--353.
[22]
S.-B. Lee, S.-W. Tam, I. Pefkianakis, S. Lu, M. F. Chang, C. Guo, G. Reinman, C. Peng, M. Naik, L. Zhang, and J. Cong. 2009. A scalable micro wireless interconnect structure for CMPs. In Proceedings of the ACM Annual International Conference on Mobile Computing and Networking (MobiCom'09). 20--25.
[23]
S. Li, J. H. Ahn, R. Strong, J. Brockman, D. Tullsen, and N. Jouppi. 2009. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proceedings of the International Symposium on Microarchitecture. 469--480.
[24]
O. Lynse, T. Skeie, S.-A. Reinemo, and I. Theiss. 2006. Layered routing in irregular networks. IEEE Trans. Parallel Distrib. Syst. 17, 1, 51--65.
[25]
R. Marculescu, U. Y. Ogras, L.-S. Peh, N. E. Jerger, and Y. Hoskote. 2009. Outstanding research problems in NoC design: System, microarchitecture, and circuit perspectives. IEEE Trans. Comput.-Aid. Des. Integ. Circuits Syst. 28, 1, 3--21.
[26]
A. K. Mishra, R. Das, S. Eachempati, R. Iyer, N. Vijaykrishnan, and C. R. Das. 2009. A case for dynamic frequency tuning in on-chip networks. In Proceedings of the MICRO. 292--303.
[27]
J. Murray, R. Hegde, T. Lu, P. P. Pande, and B. Shirazi. 2013. Sustainable dual-level DVFS-enabled NoC with on-chip wireless links. In Proceedings of the International Symposium on Quality Electronic Design. 135--142.
[28]
U. Y. Ogras and R. Marculescu. 2005. Application-specific network-on-chip architecture customization via long-range link insertion. In Proceedings of the International Conference on Computer-Aided Design (ICCAD'05). 246--253.
[29]
U. Y. Ogras and R. Marculescu. 2006. It's a small world after all: NoC performance optimization via long-range link insertion. IEEE Trans. VLSI Syst. 14, 7, 693--706.
[30]
U. Y. Ogras, R. Marculescu, and D. Marculescu. 2008. Variation-adaptive feedback control for networks-on-chip with multiple clock domains. In Proceedings of the 45th Annual Conference on Design Automation. 614--619.
[31]
P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh. 2005. Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. Comput. 54, 8, 1025--1040.
[32]
T. Petermann and P. De Los Rios. 2005. Spatial small-world networks: A wiring cost perspective. arXiv:cond-mat/0501420v2.
[33]
Z. Qian, P. Bogdan, G. Wei, C.-Y. Tsui, and R. Marculescu. 2012. A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture. In Proceedings of the 8th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'12). ACM, New York, NY, 161--170.
[34]
M. M. Sabry and D. Atienza. 2014. Temperature-aware design and management for 3D multi-core architectures. Found. Trends Electron. Des. Autom. 8, 2, 117--197.
[35]
F. O. Sem-Jacobsen and O. Lysne. 2012. Topology agnostic dynamic quick reconfiguration for large-scale interconnection networks. In Proceedings of the 12th IEEE/ACM International Symposium on Cluster Cloud and Grid Computing (CCGRID). 228--235.
[36]
L. Shang, L.-S. Peh, and N. K. Jha. 2003a. Dynamic voltage scaling with links for power optimization of interconnection networks. In Proceedings of the 9th International Symposium on the Performance Computer Architecture (HPCA).
[37]
L. Shang, L.-S. Peh, and N. K. Jha. 2003b. PowerHerd: A distributed scheme for dynamically satisfying peak-power constraints in interconnection networks. IEEE Trans. Comput. Aid. Des. Integr. Circuits Syst. 25, 1, 92--110.
[38]
L. Shang, L.-S. Peh, A. Kumar, and N. K. Jha. 2006. Temperature-aware on-chip networks. IEEE Micro. 26, 1, 130--139.
[39]
K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. 2003. Temperature-aware microarchitecture. In Proceedings of the International Symposium on Computer Architecture. 2--13.
[40]
D. J. Watts and S. H. Strogatz. 1998. Collective dynamics of ‘small-world’ networks. Nature 393, 440--442.
[41]
P. Wettin, J. Murray, P. Pande, B. Shirazi, and A. Ganguly. 2013. Energy-efficient multicore chip design though cross-layer approach. In Proceedings of DATE. 725--730.
[42]
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. 1995. The SPLASH-2 programs: Characterization and methodological considerations. In Proceedings of ISCA. 24--36.
[43]
D. Zhao and Y. Wang. 2008. SD-MAC: Design and synthesis of a hardware-efficient collision-free QoS-aware MAC protocol for wireless network-on-chip. IEEE Trans. Comput. 57, 9, 1230--1245.

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    cover image ACM Journal on Emerging Technologies in Computing Systems
    ACM Journal on Emerging Technologies in Computing Systems  Volume 11, Issue 2
    Special Issue on Reversible Computation and Regular Papers
    November 2014
    199 pages
    ISSN:1550-4832
    EISSN:1550-4840
    DOI:10.1145/2686762
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 18 November 2014
    Accepted: 01 July 2014
    Revised: 01 May 2014
    Received: 01 March 2014
    Published in JETC Volume 11, Issue 2

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    Author Tags

    1. DTM
    2. DVFS
    3. Multi-core
    4. NoC
    5. small world
    6. wireless links

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    • (2022)Design of a novel congestion-aware communication mechanism for wireless NoC in multicore systemsSignal and Data Processing10.52547/jsdp.19.1.4319:1(43-58)Online publication date: 1-May-2022
    • (2020)Exploiting Data Resilience in Wireless Network-on-chip ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/337944816:2(1-27)Online publication date: 4-Apr-2020
    • (2020)Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCsAdvanced Information Networking and Applications10.1007/978-3-030-44041-1_48(533-546)Online publication date: 28-Mar-2020
    • (2018)A General, Fault tolerant, Adaptive, Deadlock-free Routing Protocol for Network-on-chip2018 11th International Workshop on Network on Chip Architectures (NoCArc)10.1109/NOCARC.2018.8541212(1-6)Online publication date: Oct-2018
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