Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic

A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transistors and a dual threshold voltage CMOS technology are utilized to place an ...

Various fault-tolerance techniques have been proposed in recent years to tolerate the high defect rates expected in emerging nanofabrics with unconventional nano-manufacturing techniques. The proposed techniques include modular redundancy schemes that ...

This paper presents a forward body-biasing (FBB) technique for active and standby leakage power reduction in cache memories. Unlike previous low-leakage SRAM approaches, we include device level optimization into the design. We utilize super high Vt (...