research-article

Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method

Authors:

Jim Plusquellic,

Dhruva Acharyya,

Abhishek Singh,

Mohammad Tehranipoor,

Chintan PatelAuthors Info & Claims

IEEE Design & Test, Volume 23, Issue 4

Pages 278 - 293

https://doi.org/10.1109/MDT.2006.102

Published: 01 July 2006 Publication History

Abstract

Increasing leakage current makes single-threshold IDDQ testing ineffective for differentiating defective and defect-free chips. Quiescent-signal analysis is a new detection and diagnosis technique that uses IDDQ measurements at multiple chip supply ports, reducing the leakage component in each measurement and significantly improving detection of subtle defects. The authors apply regression and ellipse analysis to data collected from 12 test chips to evaluate the technique.

References

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International Technology Roadmap for Semiconductors, 2005,

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Y. Ouyang and J. Plusquellic, "IC Diagnosis Using Multiple Supply Pad IDDQs," IEEE Design&Test, vol. 18, no. 1, Jan.–Feb. 2001, pp. 50–61.

Digital Library

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C. Patel and J. Plusquellic, "A Process and Technology-Tolerant IDDQ Method for IC Diagnosis," Proc. 19th VLSI Test Symp. (VTS 01), IEEE Press, 2001, pp. 145–150.

Digital Library

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C. Patel et al. "A Current Ratio Model for Defect Diagnosis Using Quiescent Signal Analysis," IEEE Int'l Workshop Current and Defect Based Testing (DBT 02), 2002;

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C. Patel et al. "Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids," J. Electronic Testing: Theory and Applications, vol. 19, no. 6, Dec. 2003, pp. 611–623.

Digital Library

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C. Patel, A. Singh, and J. Plusquellic, "Defect Detection under Realistic Leakage Models Using Multiple IDDQ Measurements," Proc. Int'l Test Conf. (ITC 04), IEEE Press, 2004, pp. 319–328.

Digital Library

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D. Acharyya and J. Plusquellic, "Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements," Proc. 23rd VLSI Test Symp. (VTS 05), IEEE Press, 2005, pp. 433–438.

Digital Library

[8]

D. Acharyya and J. Plusquellic, "Hardware Results Demonstrating Defect Localization Using Power Supply Signal Measurements," Proc. 30th Int'l Symp. Testing and Failure Analysis (ISTFA 04), ASM Int'l, 2004, pp. 58–66.

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Digital Library

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Digital Library

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P.N. Variyam, "Increasing the IDDQ Test Resolution Using Current Prediction," Proc. Int'l Test Conf. (ITC 00), IEEE Press, 2000, pp. 217–224.

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A. Singh, "A Comprehensive Wafer Oriented Test Evaluation (WOTE) Scheme for the IDDQ Testing of Deep Sub-Micron Technologies," Proc. Int'l Workshop on IDDQ Testing, IEEE Press, 1997, pp. 40–43.

Digital Library

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S. Sabade and D.M.H. Walker, "Improved Wafer-Level Spatial Information for IDDQ Limit Setting," Proc. Int'l Test Conf. (ITC 01), IEEE Press, 2001, pp. 82–91.

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S. Sabade and D.M.H. Walker, "Neighbor Current Ratios (NCR): A New Metric for IDDQ Data Analysis," Proc. 17th Int'l Symp. Defect and Fault Tolerance in VLSI Systems (DFT 02), IEEE Press, 2002, pp. 381–389.

Digital Library

Cited By

Aarestad JAcharyya DRad RPlusquellic J(2010)Detecting Trojans through leakage current analysis using multiple supply pad IDDQSIEEE Transactions on Information Forensics and Security10.1109/TIFS.2010.20612285:4(893-904)Online publication date: 1-Dec-2010
https://dl.acm.org/doi/10.1109/TIFS.2010.2061228
Rad RPlusquellic J(2009)A Novel Fault Localization Technique Based on Deconvolution and Calibration of Power Pad Transients SignalsJournal of Electronic Testing: Theory and Applications10.1007/s10836-008-5092-025:2-3(169-185)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1007/s10836-008-5092-0
Rad RWang XTehranipoor MPlusquellic JNassif SRoychowdhury J(2008)Power supply signal calibration techniques for improving detection resolution to hardware TrojansProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509596(632-639)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509596

Index Terms

Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method
1. Hardware

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Published In

cover image IEEE Design & Test

IEEE Design & Test Volume 23, Issue 4

July 2006

64 pages

ISSN:0740-7475

Issue’s Table of Contents

Copyright © 2006.

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 July 2006

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Cited By

Aarestad JAcharyya DRad RPlusquellic J(2010)Detecting Trojans through leakage current analysis using multiple supply pad IDDQSIEEE Transactions on Information Forensics and Security10.1109/TIFS.2010.20612285:4(893-904)Online publication date: 1-Dec-2010
https://dl.acm.org/doi/10.1109/TIFS.2010.2061228
Rad RPlusquellic J(2009)A Novel Fault Localization Technique Based on Deconvolution and Calibration of Power Pad Transients SignalsJournal of Electronic Testing: Theory and Applications10.1007/s10836-008-5092-025:2-3(169-185)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1007/s10836-008-5092-0
Rad RWang XTehranipoor MPlusquellic JNassif SRoychowdhury J(2008)Power supply signal calibration techniques for improving detection resolution to hardware TrojansProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509596(632-639)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509596

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