Article

FPGAs vs. CPUs: trends in peak floating-point performance

Author:

Keith UnderwoodAuthors Info & Claims

FPGA '04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

February 2004

Pages 171 - 180

https://doi.org/10.1145/968280.968305

Published: 22 February 2004 Publication History

Abstract

Moore's Law states that the number of transistors on a device doubles every two years; however, it is often (mis)quoted based on its impact on CPU performance. This important corollary of Moore's Law states that improved clock frequency plus improved architecture yields a doubling of CPU performance every 18 months. This paper examines the impact of Moore's Law on the peak floating-point performance of FPGAs. Performance trends for individual operations are analyzed as well as the performance trend of a common instruction mix (multiply accumulate). The important result is that peak FPGA floating-point performance is growing significantly faster than peak floating-point performance for a CPU.

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Index Terms

FPGAs vs. CPUs: trends in peak floating-point performance
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
      2. Self-organizing autonomic computing
2. General and reference
  1. Cross-computing tools and techniques
    1. Performance

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Published In

cover image ACM Conferences

FPGA '04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

February 2004

266 pages

ISBN:1581138296

DOI:10.1145/968280

General Chair:
Russ Tessier
University of Massachusetts -- Amherst
,
Program Chair:
Herman Schmit
Everychip, Inc.

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 22 February 2004

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FPGA04

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FPGA04: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2004

February 22 - 24, 2004

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Salazar-Garcia CGarcia-Ramirez RRimolo-Donadio RStrydis CChacon-Rodriguez A(2021)PlasticNet+: Extending multi-FPGA interconnect architecture via Gigabit transceivers2021 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS51556.2021.9401058(1-5)Online publication date: May-2021
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Ul Sadad NAfrin AMondal M(2021)Implementation of Scalable Non-Recursive Merge Sort on FPGA2021 International Conference on Computer, Communication, Chemical, Materials and Electronic Engineering (IC4ME2)10.1109/IC4ME253898.2021.9768498(1-4)Online publication date: 26-Dec-2021
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