2009 Proceeding- General Chair:
- Paul Chow,
- Program Chair:
- Peter Cheung
FPGA 2009 is the 17th annual meeting of the ACM International Symposium on Field-Programmable Gate Arrays. As we gather again in Monterey, CA, we welcome you to this premier conference for the presentation of the latest research and advances in all areas related to FPGAs.
This year, we received 92 submissions from which we selected 24 excellent quality full papers for presentation at the Symposium (acceptance rate of 26%). This cohort of full-length papers provides a balanced program with strong contributions in the three areas of FPGA architecture (6), CAD tools (10) and applications (8).
In an effort to widen participation, we also introduce a new category known as "short papers", each having a 4-page publication, a short (5 minutes) presentation and a poster presentation. In all, eleven short papers were chosen. We will also have over 30 poster presentations that provide additional opportunities for researchers to present their work.
Delegates to this year's Symposium will enjoy an interesting pre-conference workshop on research challenges and opportunities in emerging applications, and an interesting debate during the Panel Session on Monday evening on "CMOS vs Nano: Comrades or Rivals?".
Proceeding Downloads
Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller
In this paper, a novel simultaneous multi-channel data acquisition system is proposed. Analog signals with different bandwidths are applied to an analog multiplexer with a single analog to digital converter. A novel scalable adaptive controller is ...
Performance and power of cache-based reconfigurable computing
- Andrew Putnam,
- Susan Eggers,
- Dave Bennett,
- Eric Dellinger,
- Jeff Mason,
- Henry Styles,
- Prasanna Sundararajan,
- Ralph Wittig
CHiMPS is a C-based compiler for high-performance computing (HPC) on heterogeneous CPU-FPGA computing platforms. CHiMPS efficiently supports random accesses to main memory through the many-cache memory model, enabling a broader range of applications to ...
Computation reuse in domain-specific optimization of signal recognition
Domain-specific optimizations that exploit specific arithmetic and representation formats have been shown to achieve significant performance/area gains in FPGA hardware designs. In this work, we describe an approach to domain-specific optimization that ...
The input-aware dynamic adaptation of area and performance for reconfigurable accelerator
Attaching reconfigurable loop accelerator to a processor is a promising way to improve the performance and efficiency of the system. It's usually to unroll a loop to increase the parallelism of a loop accelerator. While the higher degree a loop is ...
Implementation of the reconfiguration port scheduling on the erlangen slot machine
Despite the possibility to execute several hardware tasks in parallel on an FPGA, partial reconfiguration is sequential. There exist only one reconfiguration port which is used exclusively during the reconfiguration of a task. Single processor ...
HMMer acceleration using systolic array based reconfigurable architecture
HMMer is a widely-used bioinformatics software package that uses profile Hidden Markov Models (HMMs) to model the primary structure consensus of a family of protein or nucleic acid sequences. However, with the rapid growth of both sequence and model ...
FPGA implementation of real-time skin color detection with mean-based surface flattening
Skin color is widely used in many applications because of its merit in human-machine interactions. However, detecting skin color requires repetitive operations on all pixels in the image, similar to other vision-based applications. Since the per-pixel ...
Streaming implementation of a sequential decompression algorithm on an FPGA
This paper describes an FPGA based implementation of a real time compression algorithm used in transactions between financial institutions such as exchanges and trading houses. FIX is a protocol that has gained widespread popularity for exchanging ...
32-bit floating-point FPGA gaussian elimination
The well-known Gaussian elimination (with partial pivoting) is a widely-used algorithm, one of traditional methods for solving dense linear systems of equations (LSEs). This paper presents a hardware-optimized variant of Gaussian elimination and its 32-...
Cited By
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Liu Y, Wang Z, Che B, Chen Y, Zhao J and Yue Y (2023). FPGA versus GPU for accelerating homomorphic encryption in federated learning International Workshop on Signal Processing and Machine Learning (WSPML 2023), 10.1117/12.3014890, 9781510671928, (55)
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Xue T, Wang Y, Deng X, Zhu S, Yu Q, Su J, Chen L and Chu J (2022). GPU implementation in real-time target search for push-broom hyperspectral imagery Eighth Symposium on Novel Photoelectronic Detection Technology and Applications, 10.1117/12.2619466, 9781510653115, (3)
Index Terms
- Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays