GLSVLSI

In the post-quantum signature CRYSTALS-Dilithium algorithm, polynomial multiplication accounts for 32% of the total computation Latency. It is necessary to design a high-performance polynomial multiplication module. In this paper, we have proposed a low-...

Advanced Encryption Standard (AES) is a widely used Symmetric-key algorithm. A small characteristics improvement of AES circuits can significantly affect the system's characteristics. The Substitution box (S-box) is the only nonlinear transformation of ...

In recent years, Compute-in-memory (CiM) architectures have emerged as a promising solution for deep neural network (NN) accelerators. Multiply-accumulate (MAC) is considered a de facto unit operation in NNs. By leveraging the minimal data movement ...

To enhance the efficiency of sparse neural network models, compression methods are commonly employed to store the non-zero elements in a sparse storage format. Sparse General Matrix Multiplication (SpGEMM) is a critical computation in deep neural ...

Security, speed, and energy efficiency are critical for computing applications in general and for edge applications in particular. Digital In-Memory Computing (IMC) in SRAM cells has widely been studied to accelerate inference tasks to maximize both ...

Through silicon vias (TSVs) play a critical role in three-dimensional (3-D) packaging, facilitating the development of smaller, faster, and more efficient electronic devices crucial across various industries, such as telecommunications and computing. ...

The problem of transistor sizing is challenging due to the large design space and complex performance trade-offs. Conventional black-box optimization methods, such as Bayesian optimization, cannot leverage past experience. In this paper, we propose a ...

In the rapidly advancing landscape of computing, hardware accelerator designs are pivotal for satisfying high performance and low power demands. Systolic array (SA) architectures, tailored for general matrix multiplication (GEMM) operations, are ideal ...

Continual vertical scaling in 3D NAND flash solid-state drives (SSDs) results in larger memory blocks, causing performance degradation due to big-block management issues. Pages within a 3D NAND flash block are traditionally written using layer first ...

Value prediction is a microarchitectural technique that enhances processor performance by speculatively breaking true data dependencies. It has demonstrated improved performance in both single-threaded and multi-threaded workloads, rendering it an ...

We present a hardware-accelerated SAT solver targeting processor/Field Programmable Gate Arrays (FPGA) SoCs. Our solution accelerates the most expensive subroutine of the Davis-Putnam-Logemann-Loveland (DPLL) algorithm, Boolean Constraint Propagation (...