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Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification
In this paper we present the first Decision Diagrams (DDs) based methodology for verifying the Resistive Random Access Memory (ReRAM) synthesis process. In particular, we propose a methodology which leverages Binary Decision Diagrams (BDDs), ...
Anomaly Detection Method based on Discrete Particle Swarm Optimization for Continuous-Flow Microfluidic Biochips
Continuous-Flow Microfluidic Biochips (CFMBs) have been widely applied in various biochemical fields due to their capabilities of precise control, high integration, and automation. However, insecure supply chains enable malicious actors to tamper with ...
ControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern Generation
Due to the lengthy design cycle, generating legal, diverse and valid layout patterns artificially to expand VLSI layout pattern libraries has become an important problem to solve in order to facilitate modern design-for-manufacturability (DFM) studies. ...
IR drop Prediction Based on Machine Learning and Pattern Reduction
- Yong-Fong Chang,
- Yung-Chih Chen,
- Yu-Chen Cheng,
- Shu-Hong Lin,
- Che-Hsu Lin,
- Chun-Yuan Chen,
- Yu-Hsuan Chen,
- Yu-Che Lee,
- Jia-Wei Lin,
- Hsun-Wei Pao,
- Shih-Chieh Chang,
- Yi-Ting Li,
- Chun-Yao Wang
With the advances in semiconductor technology, the sizes of transistors are getting smaller, which has led to an increasingly severe impact of IR drop. Consequently, this trend has amplified the significance of IR drop analysis within the realm of chip ...
An Automatic Insertion Scheme of Extra Via for DSA-MP Hybrid Lithography
- Yuqin Wang,
- Cheng Guo,
- Xiaojing Su,
- Xin Hong,
- Zixi Liu,
- Xiaohuan Ling,
- Bojie Ma,
- Pengyu Ren,
- Yujie Jiang,
- Yajuan Su,
- Yayi Wei
With the continuous shrinking of feature size, directed self-assembly (DSA) has gradually become one of the leading candidates for extending the resolution of optical lithography to sub-7 nm and beyond, a DSA-based extra via (EV) insertion scheme is the ...
A P&R Co- Optimization Engine for Reducing Congestion
Placement and routing (P&R) are two crucial stages in the physical design process to optimize different objectives. For instance, placement often focuses on optimizing the half-perimeter wirelength (HPWL) and estimated congestion while routing attempts ...
Washing Optimization Method Based on Deep Reinforcement Learning for Fully Programmable Valve Array Biochips
In recent years, Fully Programmable Valve Array (FPVA) has emerged as a promising alternative for microfluidic biochips with flexible features. When two fluids flow sequentially through the same microchannel, the latter will be contaminated by the ...
Error Recovery Method Based on Deep Reinforcement Learning for Fully Programmable Valve Array Biochips
Due to manufacturing defects, chip aging, and potential malicious attacks, unexpected errors may occur in the valves of Fully Programmable Valve Array (FPVA) biochips. To address this issue, an error recovery method based on Deep Reinforcement Learning (...
MixMixQ: Quantization with Mixed Bit-Sparsity and Mixed Bit-Width for CIM Accelerators
Quantization is vital for deploying neural networks on Computing-In-Memory (CIM) based accelerators due to inherent limitations in memory devices and data interfaces’ representational capacities. However, traditional quantization algorithms often ...
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Acceptance Rates
Year | Submitted | Accepted | Rate |
---|---|---|---|
GLSVLSI '18 | 197 | 48 | 24% |
GLSVLSI '17 | 197 | 48 | 24% |
GLSVLSI '16 | 197 | 50 | 25% |
GLSVLSI '15 | 148 | 41 | 28% |
GLSVLSI '14 | 179 | 49 | 27% |
GLSVLSI '13 | 238 | 76 | 32% |
Overall | 1,156 | 312 | 27% |