DAC

New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques by making use of a global priority function. A new design-space exploration ...

The paper describes a new algorithm for the scheduling and resource allocation problem in high-level synthesis. The algorithm can not only efficiently treat flattened signal flow graphs, but also handles graphs with embedded control constructs such as ...

This paper describes an efficient approach to sparse matrix factorization on vector supercomputers. The approach is suitable for application domains like circuit simulation that require the repeated direct solution of unsymmetric sparse linear systems ...

This paper presents a theoretical framework for scheduling of subcircuit simulation in a multirate simulation environment. We show that event-driven simulation, selective-trace, and latency are subsumed by this framework.

We assume that the circuit to be ...

This paper presents several new methods for the efficient parallel simulation of VLSI circuits that contain feedback loops or “difficult” parts such as arrays, registers and pass-transistor networks. A new parallel algorithm has been developed for the ...

SoGOLaR (Sea-of-Gates Optimized Layout and Routing) is a program that generates functional cells for static CMOS circuits in the Sea-of-Gates layout style. Our generator is flexible and general enough to produce efficient layout for a wide variety of ...

We have developed a gate matrix layout synthesis tool which utilizes folding technique on both rows and columns. The conventional interval graph model and the recently proposed dynamic net-list representation can not fully depict circuit schematics such ...

This paper describes a combination transistor sizing/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's ...

The ADAM synthesis system consists of two major subsystems: the program tools which synthesize RTL designs from behavioral descriptions and the prediction tools which guide the designer in exploring the design space for a good design. In this paper, we ...

Architectural partitioning is introduced as a new phase in system level synthesis. Architectural partitioning extracts high level structure from the behavior of an architecture. This paper describes the APARTY architectural partitioner, an automatic ...

Synthesis of digital systems, involves a number of tasks ranging from scheduling to generating interconnections. The interrelationship between these tasks implies that good designs can only be generated by considering the overall impact of a design ...

This paper presents a method for the generation of controller specifications from high-level behavioral descriptions in control and timing graph form. Input descriptions may contain multiple timing constraints, asynchronous and synchronous inputs, data ...

This paper explores the suitability of the Chandy-Misra algorithm for digital logic simulation. We use four realistic circuits as benchmarks for our analysis, with one of them being the vector-unit controller for the Titan supercomputer from Ardent. Our ...

This paper presents a method for scheduling high-level blocks for functional simulation under the assumptions that circuits may be cyclic (due to element grouping), and that blocks cannot be broken down into simpler elements. The solution presented here ...

This work addresses the feasibility of mapping the COSMOS switch-level simulator onto a computer with thousands of simple processors. COSMOS preprocesses transistor networks into Boolean behavioral models, capturing the switch-level behavior of a ...

A new data parallel simulation technique of Time-Warp on the Connection Machine is presented. Our scheme handles the rollback problem of Time-Warp efficiently, and maximizes data parallelism, where the parallelism is extracted from simultaneous ...

Behavioral synthesis tools generate a wide range of designs, not all suited to one layout style. Thus there is a need for a flexible framework for mapping behavioral synthesis output onto module generators and layout tools. LASSIE provides this flexible ...

As data-path chips such as microprocessors and RISC chips become more complex, multiple stacks of data-path macros are required to implement the entire data-path. The physical decomposition of a chip into a single data-path stack, and control logic of ...

A new procedure for VLSI floor planning that minimizes routing parasitics is presented. The procedure, based on rectangular dualization, maximizes adjacency of modules that are heavily connected or connected by critical nets. Wiring macros are ...

Sea-of-gates is becoming an important design style for Application Specific Integrated Circuits (ASICs). The sea-of-gates technology offers more flexible placement and routing options not available in gate arrays. Very few systems are available today ...

The MICON system is an integrated collection of programs which automatically synthesizes small computer systems from high level specifications. The system addresses multiple levels of design, from logical through physical, providing a rapid prototyping ...

Gabriel is a retargetable software system for the development of assembly code and microcode for single or multiple programmable DSPs. It is intended to ease code development even for processors that are not easy targets for conventional compilers. Code ...

This paper presents an approach for automatic synthesis of a microprogrammed control unit from a behavioral description, incorporating two new features:

a) A rule based program to automatically design a microprogram sequencer most suited for the given ...

In an automatic routing system for macro-cell layout the wiring area is decomposed into a number of smaller regions. These regions are routed separately by a detailed router such as a channel router or a switch-box router. The position of the pins at ...

We discuss a new approach to constructing the rectilinear Steiner tree (RST) of a given set of points in the plane, starting from a minimum spanning tree (MST). The main idea in our approach is to determine L-shaped layouts for the edges of the MST, so ...

In this paper, we present a new heuristic algorithm for the classical single row routing problem. The algorithm is based on a graph theoretic decomposition scheme and uses modified cut-numbers. The algorithm was implemented in C on VAX 8200. The ...

This paper describes IRSIM, an incremental switch-level simulator for MOS transistor circuits. In IRSIM, the circuit under simulation can be modified and then incrementally resimulated. This allows error correction and circuit operation verification to ...

This paper discusses the automatic generation of high-level software models from switch-level circuit descriptions. The proposed algorithms operate directly on the hierarchical description, and incorporate information about the design such as the ...