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Parametric timing analysis and its application to dynamic voltage scaling

Published: 07 January 2011 Publication History

Abstract

Embedded systems with real-time constraints depend on a priori knowledge of worst-case execution times (WCETs) to determine if tasks meet deadlines. Static timing analysis derives bounds on WCETs but requires statically known loop bounds.
This work removes the constraint on known loop bounds through parametric analysis expressing WCETs as functions. Tighter WCETs are dynamically discovered to exploit slack by dynamic voltage scaling (DVS) saving 60% to 82% energy over DVS-oblivious techniques and showing savings close to more costly dynamic-priority DVS algorithms.
Overall, parametric analysis expands the class of real-time applications to programs with loop-invariant dynamic loop bounds while retaining tight WCET bounds.

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cover image ACM Transactions on Embedded Computing Systems
ACM Transactions on Embedded Computing Systems  Volume 10, Issue 2
December 2010
457 pages
ISSN:1539-9087
EISSN:1558-3465
DOI:10.1145/1880050
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 07 January 2011
Accepted: 01 September 2007
Revised: 01 April 2007
Received: 01 December 2005
Published in TECS Volume 10, Issue 2

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Author Tags

  1. Real-time systems
  2. dynamic voltage scaling
  3. timing analysis
  4. worst-case execution time

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