research-article

Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis

Authors:

Baris TaskinAuthors Info & Claims

ISPD '11: Proceedings of the 2011 international symposium on Physical design

Pages 131 - 138

https://doi.org/10.1145/1960397.1960426

Published: 27 March 2011 Publication History

Abstract

A novel clock mesh network synthesis approach is proposed in this paper which generates an improved mesh size with registers placed incrementally considering the timing slack on the data paths and the non-uniform grid wire placement. The primary objective of the method is to reduce the power dissipation without a global skew degradation, which is achieved through a sparse and non-uniform mesh implementation with registers incrementally placed in close vicinity to the mesh grids. The incremental register placement is based on the timing information in order to preserve the timing slack of the circuit. Experimental results show that the total wirelength (mesh grid wires and stub wires) as well as the power dissipation is reduced significantly on the clock mesh network. Specifically, the wirelength of the mesh network and the power dissipation of the clock network are reduced by 52% and 48% on average, respectively. Moreover, the global clock skew and the non-negative timing slack are preserved.

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Cited By

Cho KJang CChong J(2014)Clock Mesh Network Design with Through-Silicon Vias in 3D Integrated CircuitsETRI Journal10.4218/etrij.14.0113.125736:6(931-941)Online publication date: 1-Dec-2014
https://doi.org/10.4218/etrij.14.0113.1257
Lu JMao XTaskin B(2012)Integrated Clock Mesh Synthesis With Incremental Register PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.217349131:2(217-227)Online publication date: 1-Feb-2012
https://dl.acm.org/doi/10.1109/TCAD.2011.2173491
Taskin B(2012)Multi-voltage domain clock mesh designProceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)10.1109/ICCD.2012.6378641(201-206)Online publication date: 30-Sep-2012
https://dl.acm.org/doi/10.1109/ICCD.2012.6378641

Index Terms

Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Conferences

ISPD '11: Proceedings of the 2011 international symposium on Physical design

March 2011

192 pages

ISBN:9781450305501

DOI:10.1145/1960397

General Chair:
Yao-Wen Chang
National Taiwan University
,
Program Chair:
Jiang Hu
Texas A&M University

Copyright © 2011 ACM.

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Published: 27 March 2011

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March 27 - 30, 2011

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Cited By

Cho KJang CChong J(2014)Clock Mesh Network Design with Through-Silicon Vias in 3D Integrated CircuitsETRI Journal10.4218/etrij.14.0113.125736:6(931-941)Online publication date: 1-Dec-2014
https://doi.org/10.4218/etrij.14.0113.1257
Lu JMao XTaskin B(2012)Integrated Clock Mesh Synthesis With Incremental Register PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.217349131:2(217-227)Online publication date: 1-Feb-2012
https://dl.acm.org/doi/10.1109/TCAD.2011.2173491
Taskin B(2012)Multi-voltage domain clock mesh designProceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)10.1109/ICCD.2012.6378641(201-206)Online publication date: 30-Sep-2012
https://dl.acm.org/doi/10.1109/ICCD.2012.6378641

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