research-article

Circuit design of a dual-versioning L1 data cache for optimistic concurrency

Authors:

Adrià Armejach,

Adrián Cristal,

Osman S. Unsal,

Mateo ValeroAuthors Info & Claims

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

Pages 325 - 330

https://doi.org/10.1145/1973009.1973074

Published: 02 May 2011 Publication History

Abstract

This paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this new cache architecture, each dvSRAM cell has two cells, a main cell and a secondary cell, which keep two versions of the same data. These values can be accessed, modified, moved back and forth between the main and secondary cells within the access time of the cache. We design and simulate a 32-KB dual-versioning L1 data cache with 45-nm CMOS technology at 2GHz processor frequency and 1V supply voltage, which we describe in detail. We also introduce three well-known use cases that make use of optimistic concurrency execution and that can benefit from our proposed design. Moreover, we evaluate one of the use cases to show the impact of the dual-versioning cell in both performance and energy consumption. Our experiments show that large speedups can be achieved with acceptable overall energy dissipation.

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Cited By

Seyedi AGunnar Kjeldsberg PBirkeland R(2024)System-Scenario Methodology to Design a Highly Reliable Radiation-Hardened Memory for Space ApplicationsComputer Memory and Data Storage10.5772/intechopen.113327Online publication date: 10-Jan-2024
https://doi.org/10.5772/intechopen.113327
Seyedi AAunet SKjeldsberg P(2022)Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability RequirementsIEEE Access10.1109/ACCESS.2022.315740210(30624-30642)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3157402
Seyedi AAunet SKjeldsberg P(2019)Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)10.1109/NORCHIP.2019.8906911(1-6)Online publication date: Oct-2019
https://doi.org/10.1109/NORCHIP.2019.8906911
Show More Cited By

Index Terms

Circuit design of a dual-versioning L1 data cache for optimistic concurrency
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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cover image ACM Conferences

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

May 2011

496 pages

ISBN:9781450306676

DOI:10.1145/1973009

General Chairs:
David Atienza
EPFL, Switzerland
,
Yuan Xie
Penn State University, USA
,
Program Chairs:
Jose L. Ayala
Federal University of Pernambuco, Brazil
,
Ken Stevens
University of Utah, USA

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 02 May 2011

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GLSVLSI '11: Great Lakes Symposium on VLSI 2011

May 2 - 4, 2011

Lausanne, Switzerland

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Seyedi AGunnar Kjeldsberg PBirkeland R(2024)System-Scenario Methodology to Design a Highly Reliable Radiation-Hardened Memory for Space ApplicationsComputer Memory and Data Storage10.5772/intechopen.113327Online publication date: 10-Jan-2024
https://doi.org/10.5772/intechopen.113327
Seyedi AAunet SKjeldsberg P(2022)Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability RequirementsIEEE Access10.1109/ACCESS.2022.315740210(30624-30642)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3157402
Seyedi AAunet SKjeldsberg P(2019)Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)10.1109/NORCHIP.2019.8906911(1-6)Online publication date: Oct-2019
https://doi.org/10.1109/NORCHIP.2019.8906911
Olorode ONourani M(2015)Improving Cache Power and Performance Using Deterministic Naps and Early Miss DetectionIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2015.24940431:3(150-158)Online publication date: 1-Jul-2015
https://doi.org/10.1109/TMSCS.2015.2494043
Yalcin GSeyedi AUnsal OCristal A(2014)Flexicache: Highly Reliable and Low Power Cache under Supply Voltage ScalingHigh Performance Computing10.1007/978-3-662-45483-1_13(173-190)Online publication date: 2014
https://doi.org/10.1007/978-3-662-45483-1_13
Seyedi AYalcin GUnsal OCristal AAyala JJones AMadden PCoskun A(2013)Circuit design of a novel adaptable and reliable L1 data cacheProceedings of the 23rd ACM international conference on Great lakes symposium on VLSI10.1145/2483028.2483129(333-334)Online publication date: 2-May-2013
https://dl.acm.org/doi/10.1145/2483028.2483129
Seyedi AArmejach ACristal AUnsal OValero M(2012)Novel SRAM bias control circuits for a low power L1 data cacheNORCHIP 201210.1109/NORCHP.2012.6403113(1-6)Online publication date: Nov-2012
https://doi.org/10.1109/NORCHP.2012.6403113
Seyedi AArmejach ACristal AUnsal OHur IValero M(2012)Circuit design of a dual-versioning L1 data cacheIntegration, the VLSI Journal10.1016/j.vlsi.2011.11.01545:3(237-245)Online publication date: 1-Jun-2012
https://dl.acm.org/doi/10.1016/j.vlsi.2011.11.015
Armejach ASeyedi ATitos-Gil RHur ICristal AUnsal OValero M(2011)Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional MemoryProceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2011.67(361-371)Online publication date: 10-Oct-2011
https://dl.acm.org/doi/10.1109/PACT.2011.67

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