Cited By
View all- Kologeski AZanuz HKastensmidt F(2016)Using traffic monitoring to tolerate multiple faults in 3D NoCs2016 17th Latin-American Test Symposium (LATS)10.1109/LATW.2016.7483341(63-68)Online publication date: Apr-2016
Latency Improvement with Traffic Flow Analysis in a 3D NoC under Multiple Faulty TSVs Scenario
Authors: 
Anelise Kologeski, Henrique Colao Zanuz, and Fernanda Lima KastensmidtAuthors Info & Claims
Anelise Kologeski, Henrique Colao Zanuz, and Fernanda Lima KastensmidtAuthors Info & ClaimsAugust 2015
Article No.: 29, Pages 1 - 6
Abstract
The third dimension is becoming an attractive solution to integrate components in a single integrated circuit. Therefore, 3D Networks-on-Chip (NoCs) are usually adopted to provide fast connections between the layers by using Through-Silicon-Vias (TSVs). However, many challenges during the 3D manufacturing phase are making the circuits more vulnerable and prone to failure. This work investigates the impact on latency in 3D NoCs under multiple faulty TSVs and it proposes a technique to ensure the connectivity of the NoC under multiple faults scenario. A fault model was proposed with four different configurations to distribute multiple faulty TSVs in the 3D NoC. Three different fault tolerant scenarios were explored: the first is the original routing algorithm called Elevated-First used to avoid faulty vertical connections. The second and third scenarios are our new designs based on the use of dynamic monitors to observe the flow through the paths, in order to be able to select best alternative paths under multiple faults. Fault injection results show that it is possible to reduce the latency impact from 1x to 10x in the best case configuration by use the proposed solutions.
References
[1]
Loi, I.; Angiolini, F.; Fujita, S.; Mitra, S.; Benini, L.;, "Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.30, no.1, pp.124--134, Jan. 2011. DOI= http://dx.doi.org/10.1109/TCAD.2010.2065990.
[2]
Xie, Y.; Cong, J.; Sapatnekar, S.;, "Three-Dimensional Integrated Circuit Design (EDA, Design and Microarchitectures)", Springer, 2010.
[3]
Metzler, C.; Todri, A.; Bosio, A.; Dilillo L.; Girard, P.; Virazel, A.;, "Resistive-Open Defect Analysis for Through-Silicon-Vias," Test Symposium (ETS), 2012 17th IEEE European, May 2012.
[4]
Metzler, C.; Todri-Sanial, A.; Bosio, A.; Dilillo, L.; Girard, P.; Virazel, A.; Vivet, P.; Belleville, M., "Computing detection probability of delay defects in signal line TSVs," Test Symposium (ETS), 2013 18th IEEE European pp.1,6, May 2013. DOI = http://dx.doi.org/10.1109/ETS.2013.6569349.
[5]
Dubois, F.; Sheibanyrad, A.; Pétrot, F.; Bahmani, M.;, "Elevator-First: A Deadlock-Free Distribuited Routing Algorithm for Vertically Partially Connected 3D-NoCs", Computer, IEEE Transactions on, vol. 62, pp. 609--615, March 2013. DOI= http://dx.doi.org/10.1109/TC.2011.239.
[6]
Darve F.; ; Sheibanyrad, A. ; Vivet, P. ; Petrot, F.;, "Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links," VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on", pp. 25--30, July 2011. DOI= http://dx.doi.org/10.1109/ISVLSI.2011.59.
[7]
Kologeski, A.; Kastensmidt, F. L.; Lapotre, V.; Gamatié, A.; Sassatelli G.; Todri-Sanial, A.;," Performance Exploration of Partially Connected 3D NoCs Under Manufacturing Variability, " NEWCAS, 2013, 12th IEEE International, June 2013. DOI= http://dx.doi.org/10.1109/NEWCAS.2014.6933985.
[8]
Akbari, S. ;Shafiee, A. ; Fathy, M. ; Berangi, Reza.; "AFRA: A low cost high performance reliable routing for 3D mesh NoCs" Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 332--337, 2012. DOI= http://dx.doi.org/10.1109/DATE.2012.6176490.
[9]
Kai-Yang Hsieh; Bo-Chuan Cheng; Ruei-Ting Gu; Li, K. S.- M.;, "Fault-tolerant mesh for 3D network on chip," Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2011 6th International, vol., no., pp.202--205, 19-21 Oct. 2011. DOI= http://dx.doi.org/10.1109/IMPACT.2011.6117292.
[10]
Pasca, V.; Anghel, L.; Rusu, C.; Benabdenbi, M.;, "Configurable serial fault-tolerant link for communication in 3D integrated systems," On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International, vol., no., pp.115--120, 5--7 July 2010. DOI= http://dx.doi.org/10.1109/IOLTS.2010.5560225.
[11]
Beanato, G.,;Giovannini, P., ; Cevrero, A.,; Athanasopoulos, P.,; Zervas, M.,; Temiz, Y.,; Leblebici, Y.,;, "Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology, " IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 2, no. 2, June 2012. DOI= http://dx.doi.org/10.1109/JETCAS.2012.2193837.
[12]
Hernandez, C.; Roca, A.; Flich, J.; Silla, F.; Duato, J.;, "Fault-Tolerant Vertical Link Design for Effective 3D Stacking," Computer Architecture Letters, vol.10, no.2, pp.41--44, July-Dec. 2011. DOI= http://dx.doi.org/10.1109/LCA.2011.17.
[13]
Hwang, Y. J.; Lee, J. H.; Han, T. H.;, "3D Network-on-Chip system communication using minimum number of TSVs," ICT Convergence (ICTC), 2011 International Conference on, vol., no., pp.517--522, 28--30 Sept. 2011. DOI= http://dx.doi.org/10.1109/ICTC.2011.6082652.
[14]
Xu, T. C.; Liljeberg, P.; Tenhunen, H.;, "Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip," Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on, vol., no., pp.105--110, 13--15 April 2011. DOI= http://dx.doi.org/10.1109/DDECS.2011.5783057.
[15]
Ghidini, Y.; Moreira, M. ; Brahm, L. ; Webber, T. ; Calazans, N. ; Marcon, C.;, " Lasio 3D NoC Vertical Links Serialization: Evaluation of Latency and Buffer Occupancy," Integrated Circuits and Systems Design (SBCCI), 2013 26th Symposium on, vol., no., pp.1--6, 2--6 Sept. 2013. DOI = http://dx.doi.org/10.1109/SBCCI.2013.6644891.
Index Terms
- Latency Improvement with Traffic Flow Analysis in a 3D NoC under Multiple Faulty TSVs Scenario
Recommendations
A low-overhead soft---hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems
The Network-on-Chip (NoC) paradigm has been proposed as a favorable solution to handle the strict communication requirements between the increasingly large number of cores on a single chip. However, NoC systems are exposed to the aggressive scaling down ...
XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs
NOCS '17: Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-ChipIn this paper, we propose a method to design low latency and low energy networks for 3D Network-on-Chip (3D-NoC). Recent many-core processors require low-latency interconnection networks since the increasing number of cores limits the network ...
3D NoC with Inductive-Coupling Links for Building-Block SiPs
A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more ...
Comments
Information & Contributors
Information
Published In
August 2015
279 pages
ISBN:9781450337632
DOI:10.1145/2800986
- General Chair:
- Robson Nunes de Lima,
- Program Chairs:
- Ana Isabela Araújo Cunha,
- Calvin Plett,
- Publications Chair:
- Wagner Luiz Alves de Oliveira
Copyright © 2015 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Sponsors
- SBC: Brazilian Computer Society
- SIGDA: ACM Special Interest Group on Design Automation
- SBMICRO: Brazilian Microelectronics Society
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 31 August 2015
Check for updates
Author Tags
Qualifiers
- Research-article
- Research
- Refereed limited
Conference
SBCCI '15
Sponsor:
- SBC
- SIGDA
- SBMICRO
SBCCI '15: 28th Symposium on Integrated Circuits and Systems Design
August 31 - September 4, 2015
Salvador, Brazil
Acceptance Rates
SBCCI '15 Paper Acceptance Rate 43 of 98 submissions, 44%;
Overall Acceptance Rate 133 of 347 submissions, 38%
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- View Citations1Total Citations
- 47Total Downloads
- Downloads (Last 12 months)3
- Downloads (Last 6 weeks)0
Other Metrics
Citations
Cited By
View all- Kologeski AZanuz HKastensmidt F(2016)Using traffic monitoring to tolerate multiple faults in 3D NoCs2016 17th Latin-American Test Symposium (LATS)10.1109/LATW.2016.7483341(63-68)Online publication date: Apr-2016
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in