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MaxPB: Accelerating PCM Write by Maximizing the Power Budget Utilization

Published: 12 December 2016 Publication History
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  • Abstract

    Phase Change Memory (PCM) is one of the promising memory technologies but suffers from some critical problems such as poor write performance and high write energy consumption. Due to the high write energy consumption and limited power supply, the size of concurrent bit-write is restricted inside one PCM chip. Typically, the size of concurrent bit-write is much less than the cache line size and it is normal that many serially executed write units are consumed to write down the data block to PCM when using it as the main memory. Existing state-of-the-art PCM write schemes, such as FNW (Flip-N-Write) and two-stage-write, address the problem of poor performance by improving the write parallelism under the power constraints. The parallelism is obtained via reducing the data amount and leveraging power as well as time asymmetries, respectively. However, due to the extremely pessimistic assumptions of current utilization (FNW) and optimistic assumptions of asymmetries (two-stage-write), these schemes fail to maximize the power supply utilization and hence improve the write parallelism.
    In this article, we propose a novel PCM write scheme, called MaxPB (Maximize the Power Budget utilization) to maximize the power budget utilization with minimum changes about the circuits design. MaxPB is a “think before acting” method. The main idea of MaxPB is to monitor the actual power needs of all data units first and then effectively package them into the least number of write units under the power constraints. Experimental results show the efficiency and performance improvements on MaxPB. For example, four-core PARSEC and SPEC experimental results show that MaxPB gets 32.0% and 20.3% more read latency reduction, 26.5% and 16.1% more write latency reduction, 24.3% and 15.6% more running time decrease, 1.32× and 0.92× more speedup, as well as 30.6% and 18.4% more energy consumption reduction on average compared with the state-of-the-art FNW and two-stage-write write schemes, respectively.

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    cover image ACM Transactions on Architecture and Code Optimization
    ACM Transactions on Architecture and Code Optimization  Volume 13, Issue 4
    December 2016
    648 pages
    ISSN:1544-3566
    EISSN:1544-3973
    DOI:10.1145/3012405
    Issue’s Table of Contents
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    Publication History

    Published: 12 December 2016
    Accepted: 01 October 2016
    Revised: 01 October 2016
    Received: 01 May 2016
    Published in TACO Volume 13, Issue 4

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    Author Tags

    1. PCM
    2. power budget
    3. write scheme
    4. write unit

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    Funding Sources

    • State Key Laboratory of Computer Architecture
    • National High Technology Research and Development Program (863 Program)
    • Key Laboratory of Information Storage System, Ministry of Education, China
    • National Key Research and Development Program of China
    • Wuhan Applied Basic Research Project
    • NSFC

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    • (2018)An efficient PCM-based main memory system via exploiting fine-grained dirtiness of cachelines2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342273(1616-1621)Online publication date: Mar-2018
    • (2017)Time and Space-Efficient Write Parallelism in PCM by Exploiting Data PatternsIEEE Transactions on Computers10.1109/TC.2017.267790366:9(1629-1644)Online publication date: 1-Sep-2017
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