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ECAx: Balancing Error Correction Costs in Approximate Accelerators

Published: 07 October 2019 Publication History
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  • Abstract

    Approximate computing has emerged as a design paradigm amenable to error-tolerant applications. It enables trading the quality of results for efficiency improvement in terms of delay, power, and energy consumption under user-provided tolerable quality degradation. Approximate accelerators have been proposed to expedite frequently executing code sections of error-resilient applications while meeting a defined quality level. However, these accelerators may produce unacceptable errors at run time if the input data changes or dynamic adjustments are made for a defined output quality constraint. State-of-the-art approaches in approximate computing address this issue by correctly re-computing those accelerator invocations that produce unacceptable errors; this is achieved by using the host processor or an alternate exact accelerator, which is activated on-demand. Nevertheless, such approaches can nullify the benefits of approximate computing, especially when input data variations are high at run time and errors due to approximations are above a tolerable threshold. As a robust and general solution to this problem, we propose ECAx, a novel methodology to explore low-overhead error correction in approximate accelerators by selectively correcting most significant errors, in terms of their magnitude, without losing the gains of approximations. We particularly consider the case of approximate accelerators built with approximate functional units such as approximate adders. Our novel methodology reduces the required exact re-computations on the host processor, achieving up to 20% performance gain compared to state-of-the-art approaches.

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    Cited By

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    • (2023)Experimental analysis of the symmetry of approximate adder designs in FPGA and ASIC2023 XIII Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC60926.2023.10324275(1-6)Online publication date: 21-Nov-2023
    • (2023)Efficient Accelerator Design in High-Level Synthesis Using Approximate Logic Components2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI59464.2023.10238558(1-6)Online publication date: 20-Jun-2023
    • (2022)Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error ControlACM Transactions on Design Automation of Electronic Systems10.1145/347390927:2(1-18)Online publication date: 31-Mar-2022

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    Published In

    cover image ACM Transactions on Embedded Computing Systems
    ACM Transactions on Embedded Computing Systems  Volume 18, Issue 5s
    Special Issue ESWEEK 2019, CASES 2019, CODES+ISSS 2019 and EMSOFT 2019
    October 2019
    1423 pages
    ISSN:1539-9087
    EISSN:1558-3465
    DOI:10.1145/3365919
    Issue’s Table of Contents
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    Publication History

    Published: 07 October 2019
    Accepted: 01 July 2019
    Revised: 01 June 2019
    Received: 01 April 2019
    Published in TECS Volume 18, Issue 5s

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    1. Approximate computing

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    View all
    • (2023)Experimental analysis of the symmetry of approximate adder designs in FPGA and ASIC2023 XIII Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC60926.2023.10324275(1-6)Online publication date: 21-Nov-2023
    • (2023)Efficient Accelerator Design in High-Level Synthesis Using Approximate Logic Components2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI59464.2023.10238558(1-6)Online publication date: 20-Jun-2023
    • (2022)Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error ControlACM Transactions on Design Automation of Electronic Systems10.1145/347390927:2(1-18)Online publication date: 31-Mar-2022

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