Article

Improved alternative wiring scheme applying dominator relationship

Authors:

Chin-Ngai Sze and

Yu-Liang WuAuthors Info & Claims

ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

January 2001

Pages 473 - 478

https://doi.org/10.1145/370155.370515

Published: 30 January 2001 Publication History

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Abstract

In this paper, we present a competent algorithm to the alternative wiring problem by exploring the relationship between dominators of a target wire. Alternative wiring refers to the process of adding a redundant connection to a circuit such that a target connection will become redundant and can be removed from the circuit. The well-known ATPG-based alternative wiring scheme. Redundancy Addition and Removal for Multi-level Boolean Optimization (RAMBO), has shown its effectiveness in solving the problem in the last decade. The deficiency of RAMBO lies in its long execution time for redundancy identification among a large set of candidate alternative wires in the circuit. Implication-tree Based Alternative Wiring Logic Transformation Algorithm (IBAW) improves the speed of RAMBO by introducing an implication-tree structure for source node identification. Our approach of investigating the dominator relationship suggest that a large subset of unnecessary redundancy checks can be further avoided in order to improve the efficiency. Experiments were performed on MCNC benchmark circuits and results are compared to those of RAMBO and IBAW. Results show that our proposed algorithm improves IBAW with a 2.3 times speedup. Moreover, our implementation runs 8.8 times faster than RAMBO while solution quality is still maintained.

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Radecka KZilic Z(2002)Identifying Redundant Wire Replacements for Synthesis and VerificationProceedings of the 2002 Asia and South Pacific Design Automation Conference10.5555/832284.835390Online publication date: 7-Jan-2002
https://dl.acm.org/doi/10.5555/832284.835390
Radecka KZilic Z(2002)Identifying redundant wire replacements for synthesis and verificationProceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design10.1109/ASPDAC.2002.994972(517-523)Online publication date: 2002
https://doi.org/10.1109/ASPDAC.2002.994972

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Improved alternative wiring scheme applying dominator relationship

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ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

January 2001

662 pages

ISBN:0780366344

DOI:10.1145/370155

Chairman:
Satoshi Goto
NEC Corp., Kawasaki, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 30 January 2001

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Radecka KZilic Z(2002)Identifying Redundant Wire Replacements for Synthesis and VerificationProceedings of the 2002 Asia and South Pacific Design Automation Conference10.5555/832284.835390Online publication date: 7-Jan-2002
https://dl.acm.org/doi/10.5555/832284.835390
Radecka KZilic Z(2002)Identifying redundant wire replacements for synthesis and verificationProceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design10.1109/ASPDAC.2002.994972(517-523)Online publication date: 2002
https://doi.org/10.1109/ASPDAC.2002.994972

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Post-route optimization for improved yield using a rubber-band wiring model

A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks

Minimum-Area Wiring for Slicing Structures

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Post-route optimization for improved yield using a rubber-band wiring model

A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks

Minimum-Area Wiring for Slicing Structures

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