Article

An IDF-based trace transformation method for communication refinement

Authors:

Andy D. Pimentel,

Cagkan ErbasAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 402 - 407

https://doi.org/10.1145/775832.775937

Published: 02 June 2003 Publication History

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Abstract

In the Artemis project, design space exploration of embedded systems is provided by modeling application behavior and architectural performance constraints separately. Mapping an application model onto an architecture model is performed using trace-driven co-simulation, where event traces generated by an application model drive the underlying architecture model. The abstract communication events from the application model may, however, not match the architecture-level communication primitives. This paper presents a trace transformation method, which is based on integer-controlled data-flow models, to perform communication refinement of application-level events. We discuss the proposed method in the context of our prototype modeling and simulation environment. Moreover, using several examples and a case study, we demonstrate that our method allows for efficient exploration of different communication behaviors at architecture level without affecting the application model.

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Cited By

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Enrici AApvrille LPacalet R(2017)A Model-Driven Engineering Methodology to Design Parallel and Distributed Embedded SystemsACM Transactions on Design Automation of Electronic Systems10.1145/299953722:2(1-25)Online publication date: 4-Jan-2017
https://dl.acm.org/doi/10.1145/2999537
Stefanov TPimentel ANikolov H(2017)Daedalus: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on ChipsHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_30-1(1-36)Online publication date: 11-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_30-1
Michalska MZufferey NMattavelli M(2016)Tabu Search for Partitioning Dynamic Dataflow ProgramsProcedia Computer Science10.1016/j.procs.2016.05.48680:C(1577-1588)Online publication date: 1-Jun-2016
https://dl.acm.org/doi/10.1016/j.procs.2016.05.486
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Index Terms

An IDF-based trace transformation method for communication refinement
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies

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Published In

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 02 June 2003

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DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

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DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Enrici AApvrille LPacalet R(2017)A Model-Driven Engineering Methodology to Design Parallel and Distributed Embedded SystemsACM Transactions on Design Automation of Electronic Systems10.1145/299953722:2(1-25)Online publication date: 4-Jan-2017
https://dl.acm.org/doi/10.1145/2999537
Stefanov TPimentel ANikolov H(2017)Daedalus: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on ChipsHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_30-1(1-36)Online publication date: 11-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_30-1
Michalska MZufferey NMattavelli M(2016)Tabu Search for Partitioning Dynamic Dataflow ProgramsProcedia Computer Science10.1016/j.procs.2016.05.48680:C(1577-1588)Online publication date: 1-Jun-2016
https://dl.acm.org/doi/10.1016/j.procs.2016.05.486
Kempf TAscheid GLeupers RKempf TAscheid GLeupers R(2011)Principles of Design Space ExplorationMultiprocessor Systems on Chip10.1007/978-1-4419-8153-0_3(23-47)Online publication date: 10-Jan-2011
https://doi.org/10.1007/978-1-4419-8153-0_3
Pimentel A(2008)The Artemis workbench for system-level performance evaluation of embedded systemsInternational Journal of Embedded Systems10.1504/IJES.2008.0202993:3(181)Online publication date: 2008
https://doi.org/10.1504/IJES.2008.020299
Pasricha SDutt N(2008)On-Chip Communication Architecture Refinement and Interface SynthesisOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00009-8(341-366)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00009-8
Pimentel AThompson MPolstra SErbas C(2008)Calibration of abstract performance models for system-level design space explorationJournal of Signal Processing Systems10.1007/s11265-007-0085-250:2(99-114)Online publication date: 1-Feb-2008
https://dl.acm.org/doi/10.1007/s11265-007-0085-2
Reyes VKruijtzer WBautista TAlkadi GNúñez AGielen G(2006)A unified system-level modeling and simulation environment for MPSoC designProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131608(474-479)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131608
Pimentel AErbas CPolstra S(2006)A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction LevelsIEEE Transactions on Computers10.1109/TC.2006.1655:2(99-112)Online publication date: 1-Feb-2006
https://dl.acm.org/doi/10.1109/TC.2006.16
Kogel TMeyr HMalik SFix LKahng A(2004)Heterogeneous MP-SoCProceedings of the 41st annual Design Automation Conference10.1145/996566.996754(686-691)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996754
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Mapping concurrent applications onto architectural platforms

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A trace transformation technique for communication refinement

Simulation-based bug trace minimization with BMC-based refinement

Mapping concurrent applications onto architectural platforms

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