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National University of Singapore

Electrical and Computer Enginering

Communication-aware Heuristics for Run-time Task Mapping on NoC-based MPSoC Platforms
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    •   9  
      Energy Consumption, Hardware/Software Co-Design, Computer Software, Energy Saving
Communication-aware Design Space Exploration for Efficient Run-time MPSoC Management
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    •   6  
      Design Space Exploration, Real Time, Mathematical Model, Boolean Satisfiability
Run-time Computation and Communication Aware Mapping Heuristic for NoC-based Heterogeneous MPSoC Platforms
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      Computer Architecture, Architectural Design, Algorithm Design, Network on chip
A Hybrid Strategy for Mapping Multiple Throughput-constrained Applications on MPSoCs
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    •   6  
      Timing Analysis, System on Chip, Multiprocessor Scheduling, Throughput
Computation and Communication Aware Run-time Mapping for NoC-based MPSoC Platforms
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    •   2  
      Resource Allocation, Network on chip
A Design Space Exploration Methodology for Application Specific MPSoC Design
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    •   15  
      Iterative Methods, System Design, Space Exploration, System on Chip
Preprocessing-based Run-time Mapping of Applications on NoC-based MPSoCs
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    •   7  
      System on Chip, Resource Management, Merging, System on a Chip
Mapping Real-life Applications on Run-time Reconfigurable NoC-based MPSoC on FPGA
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    •   5  
      System Design, Case Study, Network on chip, Multiprocessor System on Chip (MPSoC)
Run-time Mapping of Multiple Communicating Tasks on MPSoC Platforms
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    •   6  
      Technology, Power Consumption, Network on chip, Multiprocessor System on Chip (MPSoC)
Efficient Task Mapping in Multi-tasking Heterogeneous MPSoC Platforms
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Mapping Algorithms for NoC-based Heterogeneous MPSoC Platforms
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    •   4  
      Digital System Design, Real Time, Network on chip, Multiprocessor System on Chip (MPSoC)
Efficient Heuristics for Minimizing Communication Overhead in NoC-based Heterogeneous MPSoC Platforms
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      Real Time, High Speed, Multiprocessor System on Chip (MPSoC)
Accelerating Through-aware Runtime Mapping for Heterogeneous MPSoCs
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Architecture-Aware Custom Instruction Generation for Reconfigurable Processors
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      Arc, Field Programmable Gate Array, Data Flow Graph, Embedded System
Rapid Design Exploration Framework for Application-Aware Customization of Soft Core Processors
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      Embedded Systems, Embedded System Design, Search Space, Logic Design
Energy Optimization by Exploiting Execution Slacks in Streaming Applications on Multiprocessor Systems
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Mapping on Multi/Many-Core Systems: Survey of Current and Emerging Trends
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Energy-Aware Dynamic Reconfiguration of Communication-Centric Applications for Reliable MPSoCs
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Incorporating Energy and Throughput Awareness in Design Space Exploration and Run-time Mapping for Heterogeneous MPSoCs
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RAPIDITAS: RAPId Design-space-exploration Incorporating Trace-based Analysis and Simulation
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