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IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 25, NO. 8, APRIL 15, 2013
Fast Sensing and Quenching of CMOS SPADs
for Minimal Afterpulsing Effects
Danilo Bronzi, Simone Tisa, Federica Villa, Simone Bellisai, Alberto Tosi, Member, IEEE,
and Franco Zappa, Senior Member, IEEE
Abstract— We present a single-photon avalanche diode (SPAD)
front-end circuitry, in a cost-effective 0.35 µm CMOS technology,
for single-photon detection in the visible wavelength range, aimed
at speeding up the sensing of detector ignition and at promptly
quenching the avalanche current buildup. The circuit allows the
reduction in detrimental effects of afterpulsing through reducing
any delays in the electronics intervention on the detector and
through a proper time-varying action of the MOS transistors on
the different SPAD’s operating conditions. The sensing time is
reduced down to a few hundreds of picoseconds, with an active
quenching transition of about 1 ns for 6 V excess bias, and a
final reset in just 3 ns.
Index Terms— Avalanche photodiodes, CMOS imagers, CMOS
technology, photon counting, photodetectors, single-photon
avalanche diode (SPAD).
I. I NTRODUCTION
INGLE-PHOTON Avalanche Diodes (SPADs) are solidstate detectors employed in several fields requiring
advanced photon counting or photon timing performance, with
sensitivities at the single-photon level in the visible or near
infrared ranges and with few tens of picoseconds time-jitter
in detecting photons arrival time, hence in reconstructing
very fast waveforms. State-of-the-art SPADs are fabricated
in custom technologies [1], [2]. However there is a growing
interest to develop SPAD imagers for 2D imaging [3] and also
3D ranging [4] or fluorescence lifetime imaging (FLIM) [5]
applications, in scaled CMOS technologies [6]–[8].
Multi-pixel photon-counting applications need high signalto-noise ratio (SNR) and wide dynamic range; to this purpose,
the SPAD detectors should have low dark count rate (DCR)
and low optical crosstalk. Dark counts can be either uncorrelated or correlated to signal photons. The former contribution
is due to ignitions caused by carriers generated through
either thermal or Shockley-Read-Hall processes. Instead the
correlated noise is caused by carriers that get trapped during an avalanche ignition and are then released igniting an
S
Manuscript received October 31, 2012; revised February 15, 2013; accepted
February 27, 2013. Date of publication March 11, 2013; date of current version
March 29, 2013. This work was supported in part by the “MiSPiA” Project,
under the ICT theme of the EC FP7 Framework, under Grant Agreement
257646.
D. Bronzi, F. Villa, S. Bellisai, A. Tosi, and F. Zappa are with
the Dipartimento di Elettronica e Informazione, Politecnico di Milano,
Milano 20133, Italy (e-mail: bronzi@elet.polimi.it; villa@elet.polimi.it;
bellisai@elet.polimi.it; alberto.tosi@polimi.it; franco.zappa@polimi.it).
S. Tisa is with Micro Photon Device srl, Bolzano 39100, Italy (e-mail:
stisa@micro-photon-devices.com).
Color versions of one or more of the figures in this letter are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LPT.2013.2251621
“afterpulse” [9], [10]. Eventually, optical crosstalk is caused
by the spurious ignition of a SPAD, due to photons emitted by
other SPADs of the array, when the hot-carriers flow during
the avalanche process triggered therein [10].
From the device standpoint, DCR can be lowered by
reducing impurities and defect concentrations, i.e., by choosing high-quality starting materials and technology processes.
Whereas crosstalk can be mitigated by placing either trenches,
opaque or doped structures between neighboring detectors.
Furthermore, from the electronic standpoint, it is possible to
reduce afterpulsing and crosstalk by minimizing the charge
amount flowing through the SPAD after avalanche ignition
[11], through the design of a proper analog front-end circuit,
with minimum capacitive loading and fast quenching [9].
We report a quenching and reset front-end, devised to
implement the aforementioned features with additional fastreset capability in order to boost SPAD performance.
II. C IRCUIT D ESIGN
The SPAD is a p-n junction reverse-biased at a voltage VPOL
above the breakdown voltage VBD , so that, when a photon
is absorbed the photogenerated carrier triggers an avalanche
current build-up; the resulting macroscopic current is sustained
by the high electric field and keeps flowing until a proper
front-end circuit quenches it.
In [12] we presented a quenching circuit devised to reduce
the anode capacitive loading and area occupation. The circuit
relied on the progressive pinch-off of the avalanche current,
until starvation, through a time-varying active load, namely
a variable-load quenching circuit (VLQC), which left very
small, though not nil, residual afterpulsing. We now present an
improved circuitry aimed at minimizing the avalanche current
flowing through the SPAD, for considerably reducing trapped
charge (leading to afterpulsing), hot-carriers (causing photon
emission and optical crosstalk) and also self- heating (yielding
distortions and detection non linearity).
Fig. 1 shows the schematics of the CMOS front-end; only
three high-voltage MOSFETs are connected to the SPAD,
each with a different role: MS senses the avalanche current
and eventually quenches it; MT flags the photon arrival, by
triggering the following electronics; MR restores the SPAD
bias conditions. Transistors MS and MT are designed with
minimum-size (W = Wmin , L = Lmin ), thus reducing loading capacitance and keeping the quiescence on-resistance
of MS to few tens of k, providing an effective initial
passive quenching [9].
1041-1135/$31.00 © 2013 IEEE
BRONZI et al.: FAST SENSING AND QUENCHING OF CMOS SPADs
777
Fig. 1. CMOS front-end. The stray capacitance CTOT includes also the
anode-to-ground and anode-to-cathode SPAD intrinsic capacitances.
The working operation is described in Fig. 2: when a
photon triggers the SPAD, the avalanche current builds up,
and the SPAD experiences a passive quenching transition due
to MS . When MT turns on and lowers node B, MS goes off
and actively pinches off the current path to ground; since
transistors MS and MT form a positive feedback loop, the
active quenching is readily assessed in about 1 ns (Fig. 4).
Shortly after node B goes below the NOR threshold, the
output node goes high causing MU to turn off (thus preventing
a short-circuit through MT ), and node D lowers to ground with
time-constant τHOLD = RHOLD × CHOLD. Since we expected a
considerable increase of afterpulses with hold-off times below
few tens of ns, we set the capacitor dimensions to 10 µm2 ,
thus limiting the minimum hold-off time to a value of 20 ns.
A single Schmitt-trigger inverter TS is exploited to both
enforce the hold-off time after each ignition (depending on its
lower threshold) and the adequate reset time (higher threshold). Moreover, TS restores the signal waveform and swiftly
enables transistor MR after node D crosses its lower threshold.
Once the low on-resistance (few tens of ohms) transistor MR
(W = 11 · Wmin , L = Lmin ) goes on, the sensing node A is
rapidly discharged (active reset) and the NOR gate forces MU
to drive node B to VDD , as soon as MT turns off. After a short
transient, node D goes high and causes MR to switch off, thus
ending the reset phase. The time elapsed from switching MS
off to switching MR on is the hold-off time, during which the
SPAD is kept off. Such hold-off time can be modified through
RHOLD , which is an n-MOS transistor, whose gate voltage is
adjustable by the user.
In order to properly simulate circuit operation (verified over
all process corners from −30 °C to 80 °C), we employed the
SPAD model reported in [13], which allowed us to foresee
non-standard operation issues and to conceive the proper circuit design. For example, Fig. 2 (dashed lines) shows how the
circuit manages a photon that hits the SPAD during reset (i.e.,
when MR is on) and ignites a second avalanche. In that situation, the second triggering prevents the anode voltage to lower
since the current keeps flowing through the SPAD until MR
goes off, i.e., as soon as node E lowers to ground; then, since
node B is at a low voltage, the NOR output rises to VDD , thus
Fig. 2.
Timing diagrams, according to simulations. Solid lines: normal
operation. Dashed lines: further operations performed when a triggering event
occurs during the reset phase.
signaling the photon arrival and starting a new hold-off phase.
This behavior ensures high detection linearity because no photon (even if absorbed during reset) is missed, hence the number
of counts correctly increases with the photon rate and eventually saturates to the inverse of the sum THOLD−OFF + TRESET ,
about 50 Mcps (counts per second).
III. E XPERIMENTAL R ESULTS
We fabricated linear arrays of SPADs, each paired to the
presented front-end in a 0.35 µm CMOS technology. The layout of each array is pad-limited and the overall dimension of a
single cell (SPAD and front-end circuit) is 160 µm × 70 µm,
whereas each quenching circuit (18 transistors) occupies an
area of 28 µm × 24 µm (Fig. 3) and each SPAD has an active
area diameter of 20 µm. This yields a fill-factor of 2.8%.
We then performed full electrical and functional tests
and characterizations. Full characterization of SPAD inherent
performances, i.e., dark-counts vs. temperature and photon
detection efficiency vs. excess bias, are reported in [17], In this
letter, instead, we focus on quenching circuit related parame-
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IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 25, NO. 8, APRIL 15, 2013
TABLE I
S UMMARY OF A FTERPULSING , DYNAMIC R ANGE (C ALCULATED AT 1 s OF I NTEGRATION T IME ) AND DCR P ERFORMANCES FOR
VARIOUS SPAD S AND Q UENCHING C IRCUITS AVAILABLE IN L ITERATURE
Tech. Node
(nm)
[12]
350
[15]
350
[16]
350
[18]
180
[7]
150
[8]
130
[19]
130
[6]
90
This Work
350
Work
Diameter
(µm)
20
10
20
8
10
8
8
6.4
20
T HOLD−OFF
(ns)
100
40
500
6
30
100
5.4
15
20
V EX (V)
QAV (pC)
AP (%)
5
3.3
4
3.5
5
1
2.6
0.4
6
1.6
0.14
0.04
1
27
23
4.5
~0
2.1
0.02
1.28
0.375
1.3
Fig. 3. Micrograph of a portion of the linear array showing the 20 µm SPAD
and the presented front-end circuit, with their respective dimensions.
Fig. 4. Cathode current waveform acquired from a scope. Inset: exponential
fitting of the quenching phase.
ters, i.e., circuit hold-off time and total charge per avalanche,
which influence afterpulsing probability and crosstalk.
At the extreme conditions of about 50 Mcps and an excess
bias voltage of 6 V above breakdown (VBD = 25 V), the
current consumption is 83 µA from VDD and 142 µA from
VPOL , mainly due to the reset current.
The avalanche current waveform was measured at the cathode, using a Tektronix MSO 4104 oscilloscope (Fig. 4): the
leading trail caused by the avalanche build-up triggers the
front-end electronics, which readily starts to starve the current;
after about 1 ns the active quenching phase ends (i.e., MS turns
off) and a change in the current slope occurs (point 1); from
now on, the current charges the capacitances only through
Peak PDE
(%)
42
40
33
20
31
28
44
55
DCR (cps)
4900
750
3000
180
230
25
410
100
25
Dynamic
Range (dB)
100
117
120
133
127
126
139
136
140
Circuit
Area (µm2 )
1500
1250
60
136
672
the SPAD internal resistance RS (self-quenching phase), so
the current exponentially decays towards a steady-state value.
Eventually, when such a value becomes low enough, the
avalanche current cannot self-sustain any longer, due to the
statistics of the avalanche process, so it happens that none
of the carriers crossing the high-field region impact ionizes
(statistical quenching (point 2))[9].
An estimation of the total avalanche charge can be made
considering Fig. 4: the first part of the transient is dominated
by an inductive response, determined by the setup topology
(lead wire, PCB trace, cable), which, soon after, evolves in
the aforementioned exponential decay.
We interpolated the data from the scope to fit the curve
(Fig. 4, inset) and we found a decay constant of 294.12 ps;
then, we measured RS (1750) with a curve tracer and we
computed the total capacitance CTOT = 167.85 fF. The overall
avalanche charge (QAV ) is CTOT × VEX = 1 pC at 6 V excess
bias when the circuit is used with the aforementioned 20 µm
diameter SPAD. We underline here that, because of the finite
bandwidth of the scope, the decay constant and, consequently,
the overall avalanche charge are overestimated.
We also measured the afterpulsing probability (AP), through
Time-Correlated Carrier Counting (TCCC) [14], by varying
both hold-off time and excess bias. The measurements were
performed at room temperature and by illuminating the SPAD
with a 570 nm LED; at this condition the SPAD has a Photon
Detection Efficiency (PDE) of 28% and a DCR of 25 cps [17].
Results are reported in Fig. 5 and they prove that SPADs have
negligible afterpulsing probability (< 1.3%). This is the lowest
value measured in a 0.35 µm CMOS technology, with the
highest excess bias and the shortest hold-off time (Table I).
Compared with more scaled technologies, the measured AP is
higher; as Table I suggests, this depends on two main factors:
lower excess bias conditions and miniaturization of SPADs and
electronics (smaller capacitances), which reduce the avalanche
charge (QAV ) and, as a consequence, the afterpulses. Nonetheless, the dynamic range (140 dB) and the peak PDE (55%) are
the highest ever reported for a CMOS SPAD, as a result of
the high maximum count rate and high excess bias condition,
low DCR and low afterpulsing.
Finally, we measured the optical crosstalk probability by
evaluating the correlation between the output signals of two
cells distant 100 µm from each other, at an excess bias voltage
BRONZI et al.: FAST SENSING AND QUENCHING OF CMOS SPADs
Fig. 5. Afterpulsing probability, at different hold-off times and excess biases,
for a 20 µm SPAD.
of VEX = 5 V. The crosstalk probability was found to be
negligible (0.03%).
Thanks to its excellent performance and small area
occupation the reported quenching circuit was integrated
within a CMOS smart pixel for indirect time-of-flight
range-finding [20].
IV. C ONCLUSION
We reported the design and the characterization of a novel
front-end for active quench and reset of SPADs, fabricated in
a standard high-voltage 0.35 µm CMOS technology.
The circuit consists of only 18 transistors and can operate
the SPAD up to 6 V above its breakdown voltage, at a
maximum counting rate of 50 Mcps.
The circuit has low stray capacitance and provides fast
mixed passive-active quenching through a prompt positive
feedback on the quenching transistor. These features considerably minimize the avalanche current flow through the detector;
hence almost vanishing afterpulsing issues, while boosting the
counting dynamic range of CMOS SPAD imagers.
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