Current status and challenges of ferroelectric memory devices

Microelectronic Engineering 80 (2005) 296–304 www.elsevier.com/locate/mee Current status and challenges of ferroelectric memory devices H. Kohlstedt, Y. Mustafa*, A. Gerber, A. Petraru, M. Fitsilis, R. Meyer, U. Böttger* and R Waser* Forschungszentrum Jülich, Institut für Festkörperforschung, IFF and the Center of Nanoelectronics for Informationtechnology CNI, Germany *Institut für Werkstoffe der Elektrotechnik, RWTH Aachen 52056 Aachen, Germany Tel: +49-(0)24616161-2994 email: h.h.Kohlstedt@fz-juelich.de Abstract We report on the state-of-the art memory devices on the basis of ferroelectric materials. The paper starts with a short survey on competitive non-volatile memory technologies and focuses then on ferroelectric memories. This includes the ferroelectric random access memory (FeRAM) and the ferroelectric field effect transistor (FeFET). Cell layouts, material aspects and CMOS compatibility as well as fabrication issues will be discussed. Beside the current research on ferroelectric memory devices we present results on the superparaelectric limit of ferroelectric materials with respect to lateral and thickness scaling. Scanning probe techniques showed ferroelectric properties in dots as small as 20 nm. Ultra thin ferroelectric films as thin as a few unit cells can be achieved on lattice matched substrates. These investigations can be considered as a guideline for the maximum achievable packaging density of FeRAMs including low power consumption. The most challenging task to achieve storage above 128 Mb, is the conformal coverage of 3-D electrodes, e.g. by atomic layer deposition (ALD). Three dimensional capacitors are mandatory to achieve sufficient charge for clear signal sensing. In addition, we present a few new concepts based on ferroresistive films, strain induced enhanced ferroelectricity, and lead-free ferroelectrics which may be relevant for the future FeRAM technology. Finally, a new challenging concept of an entire organic ferroelectric field effect transistor (OFeFET) is briefly discussed. Keywords: Nonvolatile memories; FeRAM; ferroelectrics; conformal coverage, scaling 1. Introduction There are worldwide considerable efforts to develop nonvolatile random access memories. Portable electronic equipment such as the personal digital assistant, cellular phones or digital cameras need secure and fast data transfer in combination with nonvolatile storage. Another main development route is that of contact less smart cards with multiple functions including e.g. personal banking, transport access and medical data. The market for non-volatile random access memories (NVRAMs) has been drastically increased over the last years, although by far not reaching the market volume of (volatile) dynamic random access memories (DRAMs). The required performance of NVRAMs, such as, storage density, endurance, write 0167-9317/$ - see front matter Ó 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2005.04.084 H. Kohlstedt et al. / Microelectronic Engineering 80 (2005) 296–304 and access time or power consumption are related to a particular application. Therefore it is not astonishing that a number of different NVRAMs technologies exist to fulfill all requirements. In a short survey we will summarize today’s most promising NVRAM technologies [1]. Then the paper focuses on ferroelectric random access memories (FeRAMs) and ferroelectric field effect transistors (FeFETs) highlighting the following issues: scaling, material aspects including CMOS (complementary metal oxide semiconductor) compatibility and electronic properties. In the last section we describe challenging tasks as 3-dimensional (3-D) conformal coverage of complex oxides, lead free ferroelectrics and strain induced enhancement of the spontaneous polarization Ps. Although a bit beyond of the scope of this paper, we will shortly mention the work on ferroelectric polymers including an entire polymer FeFET. 2. NVRAMs – a short survey In general we can distinguish between charged based and resistive based NVRAMs. To make this point clear, we relate this definition to the mechanism of the read operation. If the bit-line (BL) is charged via a resistor, the technology belongs to the class of resistive storage. In case the charge of a capacitor is sensed, the technology is defined as charged based storage. Resistive storage readout is non-destructive, whereas a charge based approach has a destructive readout and the bit has to be reprogrammed after a read cycle. What are the main competitors among NVRAMs? Well established technologies are Flash and EEPROMs [2]. A Flash memory cell is basically a MOSFET with an additional floating gate. Depending on the charge on the floating gate the threshold voltage of the transistor (1T-cell) is high or low and the cell acts therefore as a non-volatile storage device. The integration capability is even larger than for DRAMs. Large programming times and voltages as well as limited endurance due to high-field programming stress are the most important concerns with Flash. The advent of nano dot floating gates improved drastically the endurance [3]. A new development of so-called crested tunnel barriers (NOVORAM) [4] for the gate oxide will maybe 297 increase the programming speed and also reduce the high-field stress. Magnetic tunnel junctions (MTJs) are another promising approach. Here the information is stored via spin-dependent tunneling. The computational “0” and “1” are represented by parallel or anti-parallel alignments of the magnetization vectors of the bottom and top electrodes of an MTJ. Although this effect has been discovered already in 1975 by Juliére [5] the breakthrough for industrial applications came in 1995 by using amorphous Al2O3 as barrier and Co (or CoFe alloys) as electrodes [6]. Recently the signal amplitude R/R, was increased to about 220% by using MgO as tunnel barrier [7]. Magnetic Random Access Memories (MRAMs) are currently in the pilot line by, e.g., the consortium IBM/Infineon and Freescale. First products with MRAMs will appear this year on the market. Nonetheless, cross talk problems between neighboring cells and the relative high power consumption during programming may result in some limits for applications. In 1968, Ovshinsky presented a resistive storage device on the background of a phase-change effect [8]. The technology is called either Ovonic or (phase change) PCRAM. The principle idea is that the resistance of chalcogenics depends whether the material is in the amorphous or in the crystalline state. Programming is achieved by a particular data sequence. Ovonics are developed for example by Intel and ST Microelectronics. Since the 60`s of the last century research efforts focused on resistive switching in binary oxides as NbxOy, Al2O3, TaxOy, etc. in metal-insulator-metal configurations [9]. Nowadays, a number of new materials, ranging from polymers to complex oxides, have been successfully applied as resistive storage elements and are attracting much interest. Nonetheless, the lack of a deeper understanding of the underlying physical and chemical processes and the insufficient reliability ask for more research before these candidates can play a serious role in NVRAM technology. FeRAMs (a charged based device) and FeFETs (a resistive based device) make use of the (two) switchable remnant polarization states of ferroelectric materials by an external electric field. FeRAMs one can find today in applications as game stations or the RF tag with moderate storage densities of 256 MB. 298 H. Kohlstedt et al. / Microelectronic Engineering 80 (2005) 296–304 In the following section we will discuss the main advantages and disadvantages of FeRAMs and FeFETs [10]. Beside the above mentioned technologies there is a bunch of interesting and challenging approaches for the NVRAMs. Recently solid electrolyte electrochemical cells on the nano meter scale attracted much attention [11]. Nonetheless, in none of the existing technologies is it possible to combine all individual advantages to build a unified RAM today. A detailed overview of the status on NVRAMs can be found in text books [2, 12,13, 19]. 3. Scaling and integration density of FeRAMs Ferroelectric materials can be used with a variety of memory architectures which are closely related to conventional memories like DRAM and Flash memories. A 1T-1C ferroelectric memory cell [14] is shown in Fig.1. BL WL CBL CFE PL Fig.1 Schematic layout of a 1T-1C cell. This cell is similar to a DRAM cell with the exception of the plateline (PL) which has a variable voltage level to enable the switching of the polarization of the FeCAP, whereas its level is fixed in a DRAM. To write a “1” in the cell, the BL is set to VDD and the PL is grounded, then a pulse is applied at the wordline (WL) to activate the cell transistor. Writing a “0” is accomplished in the same manner but this time the polarities of BL and PL are exchanged to reverse the polarization of the FeCAP. Another promising architecture is the chain FeRAM (CFeRAM) [15] where the cell transistor and capacitor are connected in parallel and the cells are connected in series. Fig.2 shows two cell blocks of this memory type. BL BS1 Wl 11 Wl 10 Wl 20 Wl 21 BS2 CBL PL Fig.2 Schematic layout of a chain FeRAM. This architecture is similar to that of a NAND Flash and can achieve higher densities than the 1T-1C architecture but has a longer access time. In contrast to the conventional 1T-1C cell, accessing a CFeRAM cell is accomplished by grounding the cell’s WL and applying VDD to all other neighboring cells which short-circuits their corresponding FeCAPs. The voltage difference between BL and PL will only be dropped on the selected cell. To read the content of the memory cell first the BL is grounded, then it is made floating, which means that it effectively represents a capacitance CBL. After that the cell is selected with the help of WL. Then PL voltage is raised from GND to VDD. This would raise the voltage of BL in dependence of the polarization (data) stored in the FeCAP and the capacitance CBL according to the equations: VBL0 V B L1 A ( P s  Pr ) C BL A ( P s  Pr ) C BL A sense amplifier is used to determine the content of the memory cell. This is done by comparing the bitline voltage (BL) with a reference voltage (VR) which is ideally exactly between VBL0 and VBL1 levels. Several methods are suggested to provide the reference voltage [15]. There is a minimum voltage difference VSMIN below which the sense amplifier does not function properly which means that the voltage difference between BL and VR is not allowed to be lower than this minimum. This difference is a function of BL capacitance, the area (A), and Polarization of the FeCAP. Since the cell area scales faster than the BL capacitance and VSMIN does not H. Kohlstedt et al. / Microelectronic Engineering 80 (2005) 296–304 scale, a minimum planar cell area will be a limiting factor for scaling. This scaling limit can be overcome by using 3D ferroelectric capacitor structures or ferroelectric materials with a higher Pr [16]. Reading the cell content is destructive in FeRAMs which makes it necessary to rewrite back the data after a read cycle. Other cell architectures like the 2T-2C [10, 15] cell and the 1T cell (FeFET) are possible. In a 2T-2C cell 1 bit is stored in two capacitors that always have opposite polarizations. Despite the fact that this cell type is very reliable, it is not attractive because of the cell size which is twice the size of a 1T-1C cell. A 1T cell (FeFET) is in principle a MOSFET transistor whose gate dielectric is ferroelectric. An advantage of this cell type is that the reading operation is nondestructive but the main disadvantage is the fact that the current achievable retention time is very short to be used in a nonvolatile memory [19]. 4. Material aspects and CMOS compatibility CMOS technology is the platform for all future NVRAMs. The integration of ferroelectric oxides in CMOS processing is a task with many obstacles. Well established procedures, e.g., the hydrogen (forming gas) backend annealing in CMOS fabrication has a negative impact on the performance of ferroelectrics. It was shown that the incorporation of hydrogen into a ferroelectric leads to bonding with the apical oxygen and prevents the Ti ion from switching [17, 18]. One solution is a hydrogen barrier layer, e.g. Al2O3, which encapsulates the ferroelectric capacitor. Vice versa, the high pressure oxygen atmosphere in combination with high substrate temperatures to deposit complex oxides, lead to serious interdiffusion problems. In a stacked FeRAM cell (capacitor over bit-line, COB), as needed for highdensity storage, the capacitor is directly located on top of the MOSFET drain. The bottom electrode is electrically connected via a poly-Silicon plug. An inter-diffusion barrier (e.g., TiN, TiAl or IrOx) is mandatory to prevent the MOSFET from degradation 299 and to keep the drain-bottom electrode resistance low (< 400 µ:cm) [10]. We wish to point out that CMOS integration issues are somewhat different in case of an FeRAM and an FeFET. In an FeRAM COB cell the ferroelectric is approximately 100 nm or more apart from the MOSFET. Both devices act as physically independent elements. In an ideal FeFET the ferroelectric is in direct contact with the drain-source channel of the transistor. The ferroelectric is an active part of the transistor and the FeFET is a single device. The performance of the FeFET is therefore inextricably connected to the interface physics and electronic properties of this interface. This interface is one of the most serious problems of the FeFET. The transistor properties such as threshold voltage, saturation voltage or the C(V) curve of the gate stack are strongly influenced by localized states (e.g. dangling bonds) and impurities at the interface. Interdiffusion between the ferroelectric and Si is another bottleneck for the FeFET. Even for the native oxide SiO2 (and for high-k dielectrics) it took years to overcome all problems to achieve high performance MOSFET transistors. One possible solution in case of an FeFET is the incorporation of one (or more) buffer layer between the Si and the ferroelectric. Beside that, the band offset between Si and the ferroelectric or the buffer needs to be sufficiently large to avoid electron injection during programming [20-22]. Although the first experiments of FeFETs on Si were made back in 1974 by Wu [23], the device is still in the research state not only, but at least due to unsolved Si-ferroelectric interface problems. In Figs. 3 and 4 the most relevant integration aspects for the FeRAM stacked cell and the FeFET are summarized. 300 H. Kohlstedt et al. / Microelectronic Engineering 80 (2005) 296–304 interface improve the performance, i.e. retention, imprint and fatigue [10]. With decreasing feature size into the sub-µm range dry-etching is required to achieve vertical etch slopes. Sputter etching alone (with Argon) leads to edge slopes < 80° in Pt and complex oxides. Reactive ion etching, as the most successful technique in CMOS processing seems to have some limitation if applied to oxide materials and noble metal electrodes. The reasons are the low vapor pressure of some elements in complex oxides (e.g. Ba and Sr) as well as the chemical inertness of Pt or Ir. Ru can be chemically etched with oxygen but can lead to toxic compounds such as RuO4. Nonetheless, at least for Pt novel reactive dry-etching procedures have been developed on the basis of carbonyls (Pt(CO2)Cl2) by using Cl2 and CO as process gas at high temperatures (| 300°) and a TiN hard mask technique [10, 24, 25]. Fig.3:Schematic cross-section of an FeRAM cell and some integration aspects. Fig.4: Schematic cross-section view of an FeFET and some integration issues. Typical electrode materials of ferroelectric capacitors are Pt, Ir or Ru. These materials are refractive and either resistant to oxidation or form conductive oxides as IrOx or RuOx. It is well known that conductive oxide layers at the ferroelectric 5. Electronic properties of FeRAMs and FeFETs Ferroelectric capacitors show attractive electronic properties for NVRAM applications [10]. The switching time is below 10 ns and by far superior to Flash. The access time for COFO (Capacitor Over Field Oxide) and COP (Capacitor Over Plug) cell layouts (for the 0.35 µm generation) is 50 ns and is expected to be 15 ns for the 0.13 µm generation. Improvements in processing and materials have lead to read/write endurance cycles of 1015. The switching voltage is 3 V (0.35 µm) and will be decreased to about 1V in case the 0.1 µm FeRAM generation is realized. Regarding the thickness of the ferroelectric, e.g. PZT, it will be decreased from 200 nm to 65 nm. Moreover the Energy per bit today is approx. 1 pJ and will continuously decrease to about 0.02 pJ for the 0.1 µm generation. The data retention is approx. 10 years and thus sufficient for applications. Important failure mechanisms are fatigue, imprint and retention [13]. Imprint, i.e. the shift of the P vs. E loop and is still a problem for read out. A better understanding of the underlying physical mechanism and tailored ferroelectric materials are necessary to overcome this failure mechanism. For highly integrated FeRAMs 1T-1C CUB (Capacitor Under Bitline) cells are applied. The capacitor consists of a planar 2-D ferroelectric film. From DRAM technology it is known that a transition from a planar (2-D) to a conformal coverage H. Kohlstedt et al. / Microelectronic Engineering 80 (2005) 296–304 technology (3-D) is required to accumulate sufficient charge for the peripheral sensing amplifiers. How is the scenario for a ferroelectric capacitor? Please note that the following example is very simple and does not consider details of the different sensing schemes. The aim here is to get some idea at which generation a transfer from a 2-D to a 3-D technology is needed. If we assume a minimal capacitance of 30 fF and a switching voltage of 1 V we get an amount of 3 x 10-14 C on the bit line for sensing. Since n = q/e this corresponds to approx. 20.000 electrons. We compare this number with the maximum available charge from ferroelectric capacitors assuming the following parameters: A = 100 x 100 nm2 (planar) and P = 10µC/cm2. With q = P A we get a charge of 10-15 C or 6.000 electrons on the bit line which is not enough for sensing. A 3-D layout as shown in sketch (Fig. 5) leads to a 5 times larger area on the same footprint. This leads to 30.000 electrons, so that the signal detection is possible. Fig.5 3-D sketch of a ferroelectric capacitor including conformal coverage. The situation for the FeFET is somewhat different. The FeFET needs materials with a low Pr (< 2 µC/cm2) to influence the source drain conductivity of the transistor. Often subloops are used to reach this low Pr values and in addition to avoid electric breakdown of the buffer [19]. 301 6. Physical limitations of ferroelectric oxides The aggressive down-scaling of FeRAM capacitors currently meets the basic studies on the size limit of ferroelectric oxides. FeRAM technology is accompanied by considerable efforts of various research groups to fabricate nanometer dots and understand the superparaelectric limit of ferroelectrics [26-28]. This research can be understood as a guideline for the ultimate scaling of FeRAM cells. Nonetheless, fundamental studies are typically performed on model systems (which sometimes appear artificial) to reduce the influence of parasitic effects. Therefore, the relevance of the obtained results has to be carefully compared with the requirements of the down scaling procedure of FeRAM technology. In the last years tremendous progress has been made to fabricate nanometer sized ferroelectric dots and ultra thin ferroelectric films. Self assembly and template assisted methods have been successfully developed to produce dot sizes from below 50 nm down to 10 nm and were characterized by advanced piezo-response force microscopy (PFM) [26 – 28, 32]. Actual 20 nm dots show ferroelectricity. Whether bottom-up techniques will enter future FeRAM technology is not certain. Encouraging is the fact, that self assembly techniques for poly-Si will be used to produce discrete floating gates for Flash transistors [3]. Thickness scaling of ferroelectric films is of special importance because highly integrated FeRAMs require low switching voltage (| 1 V). The Argonne group deposited ultra thin films of PbTiO3 with only 3 unit cells thickness and studied their structural properties in-situ by a sophisticated synchrotron facility [29]. Ferroelectricity was proved for PZT films of 4 nm by electric force microscopy EFM [30]. Good hysteresis loops have been observed for BTO films down to 12 nm and for PZT films even down to 8 nm [31]. The results were obtained on epitaxial films on single crystal substrates and epitaxial electrodes (i.e. SrRuO3 on SrTiO3 100). Moreover in epitaxial films ultra small areas have been polarized and switched by conductive AFM. Integration densities as high as 40 Gbit/cm2 were estimated [32]. In principle the millipede concept is therefore applicable to ferroelectric materials (see Chapter 28 in ref. [19]). 302 H. Kohlstedt et al. / Microelectronic Engineering 80 (2005) 296–304 The actual research focuses on the important influence of mechanical (strain) and electrical boundary conditions (screening effects) of ferroelectric capacitors. This includes also the study of individual defects [47] (e.g. grain boundaries or interfacial dead layers) to understand their local influence in ferroelectric materials. In principle these exiting results mean that there is still room for a further down scaling of the minimum feature size in FeRAMs. 7. Future tasks in ferroelectric memories In this section we describe several important requirements and possible tasks for future ferroelectric memories. (a) Evolution of the current FeRAM technology A consequence of cell scaling will be the development of ultra thin PZT films or layered oxides such as SrBi2Ta2O9 down to 10 nm to obtain a sufficient low coercive voltage and to lower power consumption. This approach is not easy since the coercive field increases with decreasing ferroelectric layer thickness in most cases. The thickness range of 10 nm (and below) was in the last years dominated by fundamental research aspects as the superparaelectric limit of ferroelectrics [29,30,33]. Hereby single crystals are used as substrate and therefore the obtained (indeed promising) results cannot be directly transferred to novel metal electrodes and a CMOS environment without considerable improvements in processing. Moreover to achieve high integration density in FeRAMs it is essential to apply a 3-D conformal coverage technique by using state-of-the art and advanced MOCVD technology (i.e. atomic layer deposition ALD or pulsed MOCVD [35]) to get a sufficient large area. The strict requirement for the minimum cell capacitance (30 fF) is needed to achieve an unambiguous signal sensing. Estimations show that 10 nm PZT including 3-D conformal coverage are necessary for 128 Mb chips and beyond. The conformal coverage of a 3-D electrode with a ferroelectric not only has to be uniform in thickness but should also exhibit uniform properties with respect to stoichiometry, nucleation and domain switching across the entire capacitor area. In addition an either random or 111 orientation is preferred to provide a homogeneous switching across the entire 3D capacitor. These issues are maybe the most challenging tasks to overcome in order to achieve highly integrated FeRAMs. Pb compounds are widely used in ferroelectric memories. Concerning the electrical characteristics PZT is a suitable candidate for high-integration and has won so far the race against SBT. On the other hand, the European Union could forbid an electronic with lead contents by law soon due to health and environmental reasons. It is likely that other (lead free) ferroelectrics will be considered and the interest in SBT will be renewed. Recently, new lead free compounds as (K0.44Na0.52Li0.04)(Nb0.86Ta0.10Sb0.04)O4 [35] or BiFeO3 [36] were successfully prepared. The former even shows a piezoelectric coefficient larger than that of PZT (52/48). This compound could replace PZT in actuators or sensors. Whether this rather complex material can be integrated in thin film form in FeRAMs or not is questionable. BiFeO3 and BiMnO3 [36] appear far more realistic for these purpose. Both show a large spontaneous polarization and are possible candidates for lead-free FeRAMs. BiFeO3 is multiferroic and exhibits ferroelectric and also magnetic properties. Whether this combination (ferroelectric-ferromagnetic) is useful for memory application or not is unclear. (b) New approaches In this sub-section we focus on rather unconventional approaches for advanced FeRAMs and FeFETs. An interesting possibility for lead-free FeRAMs is the use of strained enhanced ferroelectric properties. It is known that the phase transition temperature and the spontaneous polarization can be increased for tetragonal ferroelectrics under biaxial compressive strain conditions [37]. Recently Eom, Schlom and coworkers showed well defined hysteresis loops of BaTiO3 with 500°C ferroelectric transition temperature and a 250% higher remnant polarization than in bulk BaTiO3 single crystals at room temperature [38]. The strain engineering was achieved on exotic and well selected (with respect to the out-of-plane lattice parameters) substrates as DyScO3 and GdScO3 single crystals. These results H. Kohlstedt et al. / Microelectronic Engineering 80 (2005) 296–304 are encouraging but it is not a straightforward task to implement strained BaTiO3 with those superior parameters into CMOS technology. Ferroelectric capacitors are charge based devices. As explained above, 3-D deposition techniques are mandatory for high integration densities at some point and extremely difficult technological problems have to be solved by MOCVD. This case is one of the biggest advantages for resistive based NVRAMs. It is believed that the scaling of resistive memories (on the basis of MIM junctions) will be a planar 2-D technique even down to the nm-scale. Simple crossbar arrays, without selection transistor may led to a high packing density. During the last years there was an interesting ongoing debate whether ferroresistive materials or the so-called ferroelectric Schottky diodes are an alternative to ferroelectrics for NVRAMs [39,40]. The term ferroresistive means the following: At first a ferroelectric is a perfect insulator. Any kind of leakage current is considered as a parasitic effect which reduces the device performance of FeRAMs in many respects (power consumption, switching, retention etc). M Di Fe M Ps M Ps < 0 RH >0 x RL Fig.6 Principle of an FRRAM; Fe: ferroelectric (slightly conductive), M:metal, Di: dielectric (slightly conductive) [41].M is the potential. On the other hand if we assume a coexistence of a (slightly) conductive film and ferroelectricity it may be possible to alter the resistance between two resistance states through changing the polarization 303 direction of the ferroelectric by applying an external field. We wish to point out that this ferroresistive RAM (FRRAM) has a non-destructive readout and scaling into the Gbit range is possible with a planar technology because remnant polarizations of 1 µC/cm2 or less are sufficient. One possible realization of a FRRAM is schematically shown in Fig. 6 together with the barrier potential in dependency of the polarization direction [41]. The device resistance shows two (low and high) states, depending on the polarization direction, which represent the logical “0” and “1” with a nondestructive readout. The appropriate doping and the kind of current transport through the device are still unsolved. Another interesting approach are so-called ferroelectric tunnel junctions (FTJs). This concept is based on the idea that direct tunneling through ultrathin ferroelectric tunnel barriers depends on the polarizations state. Indeed, several phenomena as strain, microscopic interface effects and incomplete screening of the ferroelectric bound charge may lead to a resistive switch [50]. Ferroelectricity is found in various material classes and is not restricted to complex oxides alone. PVDF (polyvinylidene fluoride copolymer) for example exhibits ferroelectric properties [49]. By considering the fast-paced developing of polymer electronics in general it is likely that ferroelectric polymers can play a vital role in this exciting field. An interesting approach is the incorporation of ferroelectric polymers as gate oxides in FeFETs. Ferroelectric polymers are deposited at room temperature so interdiffusion is not a problem and buffer layers are not needed. Experiments have been performed on Si substrates [42-44] and recently entire organic field effect transistors were successfully built [45,46]. This could be an important step towards a cheap and flexible non-volatile memory. On the other hand the switching time will be by far lower than in case of oxide FeRAMs and therefore the market targeted will be different. 7. Conclusions FeRAMs are a well developed technology. The maximum integration density will depend very much 304 H. Kohlstedt et al. / Microelectronic Engineering 80 (2005) 296–304 on the successful implementation of a 3–D (conformal) coverage technology and the atomic layer deposition technique. Serious competitors are resistive storage memories which on the other hand have to prove their compatibility with CMOS and their application in the “real” world. For the FeFET severe interface issues between Si, the buffer and/or ferroelectric have to be overcome and/or new, unconventional concepts have to be developed. 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