Analytical Modeling and Staggered-Planar Structural Analysis for Organic Field Effect Transistor Brijesh Kumar1, Poornima Mittal2, Shradha Saxena1, B. K. Kaushik1 Y. S. Negi1 and G. D. Varma1 1 Indian Institute of Technology, Roorkee, India 2 Graphic Era University, Dehradun, India 1 (bk228dpt; ashrapph; bkk23fec; ynegifpt; gdvarfph)@iitr.ernet.in; 2poornima2822@gmail.com Abstract-This paper presents device physics based on electrical modeling of staggered and planar structures of Organic Field Effect Transistors (OFETs). It is preferable to have compact dc models that can be used in simulations to forecast and optimize performance of OFETs. Since a unified compact model is not sufficient to derive all characteristics using materials and fabrication processes, therefore, several analytical models have been proposed. For each model, an efficient estimation of model equation is undertaken in terms of dependent and independent variables, model parameters and substantial operating parameters in order to make better mapping of model equations into a corresponding device circuit. Subthreshold current, channel length modulation and channel mobility trends are described. Finally, comparative analysis of staggered and planar structures has been analyzed using SILVACO ATLAS 2-D numerical device simulator. Observations reveal that OFET with staggered structure exhibit superior performance as compared to those with planar structure in terms of mobility, contact resistance and current. Keywords-Analytical modeling, Device simulation, Compact model, Staggered and planar structure, Organic field effect transistor . I. INTRODUCTION There has been a lot of progress in the last decade on producing smarter and smaller organic devices with high performance. Organic electronics is an enabling technology for a wide range of applications. In particular from the radio frequency identification (RFID) tags, large area sensors and flexible displays applications point of view. Organic Field Effect Transistors (OFETs) which consists of conducting polymers or small molecules as an active semiconductor have shown high potential in terms of performance and fabrication process at low cost flexible devices [1]. OFETs fabricated at low temperatures allow use of flexible plastic substrates and spin coating process for fast and inexpensive coverage of large areas. As a result of the expansion of application of TFT devices, compact TFT models are required and that are suitable to be implemented in advanced TCAD simulators [2]. There are numerous possible reasons for undertaking device modeling. Possibly the most common device modeling objective is to understanding the physical nature of device operation and optimization. Modeling 978-1-4673-1318-6/12/$31.00 ©2012 IEEE presented herein is useful for the explanation of non ideal device characteristics, which are often encountered in development of novel OFET materials and device structures. Thus model discussed herein will find use in development of organic and polymer based emerging organic device technologies. It is well known that metal oxide semiconductor field effect transistors (MOSFETs) have a unified compact model. But due to several factors such as contact resistance effects, bias dependent mobility, structure of TFT, use of various materials for organic semiconducting thin film, gate dielectric, substrate, contact electrodes, and many other factors, due to which there exist many differences between different OFETs. Therefore it is not possible to define a unified compact model for OFETs [3]. This paper presents basic structures and unified standard model for OFETs, which depend upon common points of various models and have analogous to compact model used for MOS transistors. The topics included in this paper are as follows. The present section I introduces the contents of the paper. Section II describes basic difference between staggered and planar structures. Section III describes basic requirements for OFETs compact model and its comparison with MOSFETs. OFET charge drift model is explained in section IV. OFETs charge drift model to compact DC model discussed in section V. Effect of structures on performance of organic transistor and conclusion is drawn in section VI and VII respectively. II. STAGGERED AND PLANAR STRUCTURES OF OFET Source Gate Drain Au Pentacene Au Insulator (SiO2) Gate (n+ Si) Substrate (a) Drain Source Gate Au Au Pentacene Insulator (SiO2) Gate (n+ Si) Substrate (b) Figure 1. Two OFET structures used in 2-D numerical device simulation. (a) Planar structure (b) Staggered structure. semiconductor [21]. OFETs adopt the structure of thin film transistor (TFT), which has proven it’s flexibility with low conductivity materials. The performance of planar structure are usually lower than staggered structure of OFETs because of higher contact resistance [21] which is either due to interface contact barrier or by poor morphology of the organic semiconductor layers around prepatterned source and drain contact metal layers [4, 5]. COMPACT MODEL FOR ORGANIC FIELD EFFECT TRANSISTORS III. Despite many variations, there are some common points in the behavior of different OFETs, and the most common point among all models is mobility enhancement at higher gate overdrive voltage. Thus compact model based on this fact, must represent behavior of organic transistors. Further common points comprise that most of OFETs has symmetric structures, that means drain and source are interchangeable; therefore compact model must be symmetrical. Compact model for organic transistors should be upgradable, reducible, easily derivable and analogous to MOSFETs [2]. Organic transistor equation can be expressed by analogous equation (1) to conventional transistor. This analogous equation further divided in equation (2) and (3) which are defined unified standard model and dc operation analogous to MOSFETs above threshold. All compact dc models can be reduced to these equations [2]. Analogous OFETs drain current expression can be defined by standard transistor equations [17]. (1) For linear regime, Vds <= (Vgs – Vt) (2) For saturation regime, Vds > (Vgs – Vt) (3) where drain current is Ids, channel width is W, channel length is L, mobility is µ, and Vgs, Vt and Vds are gate, threshold and drain voltages, respectively and Ci is capacitance of insulator. -5 1.2 x 10 1 Drain Current, Ids (A) An OFET is transistor made up of thin film current carrying organic semiconductor (OSC), an insulator layer and three electrodes. Two of the electrodes, source (S) and drain (D) are in direct contact with organic semiconductor and the third, gate (G) electrode is isolated from semiconductor by dielectric insulator. OFETs are based on multilayer structure whose electrical properties are affected by characteristics of different material layers, interface between them and device structures [12]. Structures can be categorized into four types of basic structure of organic transistors. First it can be divided into top and bottom gate structures with respect to position of gate electrode. Further depending on the position of contact electrodes with respect to active semiconductor and dielectric layer such as bottom gate planar structure, bottom gate staggered structure, top gate-planar structure and top gate-staggered structure. Bottom gate structures are built in majority for existing OFETs since deposition of organic semiconductor on insulator is much easier than the reverse due to fragile nature of organic semiconductors. Furthermore, bottom gate has two configurations. One is called a planar structure when the gate is at the bottom, above which the insulator layer is deposited. Source and drain contacts are formed above the dielectric layer and finally organic semiconductor layer is deposited on the top of the structure as shown in Fig. 1(a). Planar structure is advantageous because the methods involving solvents and thermal treatments can be safely employed to build the gate dielectric and contacts without harming the semiconductor layer [15]. Moreover, planar structures have an advantage of utilizing standard lithographic techniques straightforwardly for obtaining short channel length devices [5]. However, these devices usually suffer from higher contact resistances because of smaller effective area for charge carrier injection [12]. Other is called staggered structure when contacts on top are deposited through shadow mask where as for planar structure formation microlithography technique is used [4]. The staggered structure OFET fabricated using shadow mask technique results in relatively large channel length devices as shown in Fig. 1 (b) [18]. However, for same semiconductor and dielectric materials, the contact resistance and mobility are better in staggered devices. The better mobility for staggered OTFT is due to less contact resistance than that of planar [5]. OFETs mobility in planar device structure is generally observed to be lower than to staggered structure device. The reasons for this difference is often explained by the large metal-organic semiconductor contact resistance due to interface contact barrier and poor morphology of semiconductor film around the already patterned source and drain contacts [15]. Organic semiconductor films grown on metal often have inferior properties as compared to those grown on an insulator [19]. In staggered structure, lower contact resistance and larger injection area enables higher currents for the same applied voltages in comparison to planar structure [20]. The performances of organic devices are depending on their structures, fabrication processes, organic materials and interface between contacts, dielectric and organic 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5 2 Drain Voltage, Vds (V) 2.5 3 Figure 2. Output characteristics of organic field effect transistor compact model. Fig. 2. shows output characteristics of organic field effect transistor compact model which is comparable to standard transistor characteristics. Various parameters considered to draw output characteristic are as follow: µm, Ci=800 nF/cm2, µ=2.0 cm2/V.s, Vt= 0.1 V, L=10 and W=100 µm. IV. TYPICAL CHARGE DRIFT MODELFOR ORGANIC FIELD EFFECT TRANSISTORS Systematic evaluation of OFET Models, the bias enhancement of mobility has to be found most common point among all models and it can be rooted in compact models in a functional form of μ ∝ (Vgs – Vt )a, a > 0, where a is the mobility enhancement factor [2, 3]. The origin of OFETs standard charge drift model is specified on basis of charge drifting, and current per unit width in organic transistors are represented by standard equation similar to [17]: | | (4) Figure 4. Characteristics between drain current (Ids) and mobility enhancement factor. On integration of (8) along channel length L at distance k as in [6, 10]. Where |Ek| = ∂Vk/∂k is magnitude of electric field, at a given position k in the channel, 0 ≤ k ≤ L. μk is the field effect mobility, and area charge density qk is specified by the expression q (5) where voltage applied at gate is Vgs , threshold voltage is Vt and Vk is the semiconducting film potential of OFETs and Ci is capacitance of insulator. According to M. Shur at el. and M. Vissenberg at el. [10, 11] mobility model can be described by (6) By putting the value of (5) and (6) in (4) simplified as (7) (8) -5 6 Drain Current, Ids (A) 5 4 x 10 Vgs=1.2V Vgs=1.5V Vgs=1.8V Vgs=2.1V Vgs=2.4V 2 1 0.5 1 1.5 2 Drain Voltage, Vds (V) 2.5 3 Figure 3. Organic field effect transistor output characteristics for charge drift model. (10) where Vs and Vd is voltage of conducting channel at source and drain side, respectively. The analogous expression for OFET standard charge drift model is specified as (11) Above equations are defined for n-channel OFETs. Most of the OFETs are fabricated based on pentacene which is p-type material. To defined equation for p-channel organic transistor the polarities of currents and voltages have to be inverted. Various parameters such as µ0= 1.64 cm2/V.s, Vt=0.1V, a=2, W=100µm, L=10µm, Ci=800nF/cm2, and VS=0.105V are considered to draw output characteristic for OFET charge drift model as shown in Fig. 3. The effect of mobility enhancement factor “a” on drain current is shown in Fig. 4. It can be seen that as mobility enhancement factor increases, drain current is also increases. V. 3 0 (9) OFET CHARGE DRIFT TO COMPACT DC MODEL In order to emulate electrical characteristics of valid OFETs, new approaches have introduced such as by adding sub threshold operation and channel length modulation in standard charge drift model, a compact dc model has obtained which is applicable to all regimes of operation of transistor [2, 3]. Sub threshold region is defined using an asymptotically interpolation function [7, 8] in (11), which comes as [17] (12) Here V = Vds or V = Vs, function f(Vgs, V ) can be considered as overdrive voltage (Voverdrive) which is expressed by , ln 1 The characteristic of channel length modulation can be added in TFT general model by introducing channel length modulation coefficient b which is represented in equation (15). ∆ 1 For sub threshold regime, when 1 | | (15) Rewriting standard charge drift model ∆ (16) For above threshold regime, when (13) On putting (14) in (15), generates new concept which is expressed by equation (17) On substituting the function value from (13) to (12), gives 1 2 (17) (14) where Vsub is sub threshold slope voltage that is linked to steepness of sub threshold characteristics [9] of TFT. Fig. 5. shows the sub threshold characteristics for (14) with model parameters nF/cm2, µ0=1.64 cm2/V, Vt= 2.0 V, a=0.190, W=100 µm, L=10 µm, Ci=800 nF/cm2 , Vsub=800 mV, and VS= 0.105. Subsequently Fig. 6. shows effect of channel length modulation on output characteristic of compact DC model (17) for various parameters such as Vt= 0.3 V, a =1.1 and b = 0.15 %/V, VS= 0.105, W=100µm, L=10µm, Ci= 800 nF/cm2, µ =1.60 cm2/V. Further it is found that ΔL/L is a sub linear function of drain bias, having a decreasing slope ∂ln (Ids)/∂Vds when Vds increases above the saturation voltage VSAT ≈ (Vgs – Vt ). VI. -6 Drain Current, Ids (uA) -6.5 -7 -7.5 -8 Vgs=0.3V Vgs=0.6V Vgs=0.9V Vgs=1.2V Vgs=1.5V -8.5 -9 -9.5 0 0.5 1 1.5 2 Drain Voltage, Vds (V) 2.5 3 Figure 5. Sub-threshold characteristics for organic field effect transistor. -5 6 Drain Current, Ids (A) 5 4 x 10 Vgs=1.2V Vgs=1.5V Vgs=1.8V Vgs=2.1V Vgs=2.4V Most important physical device parameters value [14] used in staggered and planar structure analysis are shown in table I. The properties of pentacene organic semiconductor material used in simulation are shown in table II. Consequently bottom gate analysis has been performed for staggered and planar OFET structures with Silvaco ATLAS 2-D numerical device simulator setup. Out of these two structures, one structure is referred as planar and other as staggered structure, as shown in Fig. 1 (a) and Fig. 1 (b), respectively. Further Fig. 7 to Fig. 10 shows the simulated output and transfer characteristics of staggered and planar structures respectively. Observations reveal that OFET with staggered structure exhibit superior performance as compared to those with planar structure in terms of drain current, mobility, threshold voltage, contact resistance and current on-off ratio. TABLE I. PHYSICAL PARAMETERS FOR STAGGERED AND PLANAR OFETS. 3 S.No. 2 1 0 ELECTRICAL CHARACTERISTICS OF OFET STRUCTURES 0.5 1 1.5 2 Drain Voltage, Vds (V) 2.5 3 Figure 6. Output characteristics for channel length modulation with maximum drain current (Ids) value is 5.4 x 10-5 A . Name of device parameters Parameter values 1 Pentacene semiconductor thickness (tP) 25 nm 2 Al2O3 insulator layer thickness (tox), 5 nm 3 Aluminum gate thickness 10 nm 4 Gold source/drain contact (tS, tD), 20 nm 5 Channel width (W) 100 µm 6 Channel length (L) 10 µm TABLE II. PROPERTIES OF ORGANIC SEMICONDUCTOR MATERIALS FOR STAGGERED AND PLANAR OFETS [5]. S. No. Pentacene properties Values 1 Energy band gap 2.8 ev 2 Density of conduction band 2.8×1021 cm-3 3 Density of valance band 2.8×1021 cm-3 4 Permittivity 4.0 5 Acceptor doping concentration 5.7×1017cm-3 6 Electron affinity 2.4ev The advantage of top contact or staggered structure is lower contact resistance, due to larger effective area for injecting charge into the semiconductor channel and corresponds to gate and drain and gate source overlap areas. The main disadvantage of staggered configuration is that the charges have to transport from the source to the channel through an undoped highly resistive semiconductor layer. Thus, the experimentally obtained mobility and threshold voltage of OFETs is thickness dependence [13]. On the other hand, since photolithographic patterning of source and drain contact in staggered is not possible because solvents can damage the organic semiconductor (OSC) thin film layer. They should be deposited on top of organic semiconductor typically through a shadow mask technique. Moreover planar structure is advantageous because the methods involving solvents and/or thermal treatments can be safely employed to prepare the gate dielectric and contacts without harming the semiconductor layer [13, 15]. Moreover, planar structures have an advantage of utilizing standard lithographic techniques straightforwardly for obtaining short channel length devices. However, these devices usually suffer from higher contact resistances because of smaller effective area of charge carrier injection [5, 16]. Figure 8. Transfer characteristics of OFET with top contact or staggered structure Figure 9. Output characteristics of OFET with bottom contact or planar structure Figure 10. Transfer characteristics of OFET with bottom contact planar structure. VII. CONCLUSION Figure 7. Output characteristics of OFET with top contact or staggered structure. The difference in drain current and characteristics performance parameters such as threshold voltage, mobility and contact resistance for planar and staggered structure devices are not only because of device structures, but also, method of fabrication process, way of modeling and material properties. OFETs analytical model has been developed in which mobility increases as gate bias increases. Further on the basis of this fact TFT charge drift model is proposed which is comparable to conventional transistor. Moreover its characteristic parameters have well defined physical interpretation for OFETs. Subsequently OFET compact DC model has been derived by entrenched the concept of sub threshold region and channel length modulation in organic transistor charge drift model. Analytical models discussed herein will find use in the improvement of current, future and emerging OFET technologies. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] V i e w C. D. Dimitrakopoulos and P. R. L. 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