MOS Current Mode Logic

This paper explores the resistance of MOS Current Mode Logic (MCML) against attacks based on the observation of the power consumption. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from Differential Power Analysis and similar side-channel attacks. In order to demonstrate the effectiveness of different logic styles against power analysis attacks, two full cores implementing the AES algorithm were realized and implemented with CMOS and MCML technology, and a set of different types of attack was performed using power traces derived from SPICE-level simulations. Although all keys were discovered for CMOS, MCML traces did not presents characteristic that can lead to a successful attack.

In this paper, we present three digital multiplier architectures capable of operating in the gigahertz range, based on MOS Current Mode Logic (MCML) style. A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, (3x2) counter (full adder), [4:2] compressor, and master-slave flip-flop were designed and optimized for high-speed operation. Using these gates, we propose three different 8-bit MCML binary-tree multiplier architectures and compare their performance in terms of latency, throughput (number of multiplications per second) and power consumption. According to our simulation, the fastest multiplier targeting for TSMC 0.18 µm CMOS technology attains a throughput of 4.76 GHz or 4.76 Billion multiplications per second and a latency of 3.8 ns.

In this paper, we present three digital multiplier architectures capable of operating in the gigahertz range, based on MOS Current Mode Logic (MCML) style. A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, (3x2) counter (full adder), [4:2] compressor, and ...

In this article, we present a new method of realization of a four-quadrant analog multiplier using operational amplifiers (OP-AMPs) and MOSFETs. The realisation is based on the quadric nature of current of MOSFET operating in triode region. The multiplier can be derived from the proposed configuration with using either bipolar or complementary metal-oxide-semiconductor (CMOS) OP-AMPs. It can be used effectively with a wide range of supply voltages down to ± 1 V and can multiply over the full scale of the supply voltage if the OP-AMPs used are rail-to-rail low voltage OP-AMPs. The performances of the proposed multiplier are tested through PSPICE (Cadence 16.6) simulation using TSMC 0.35 µm CMOS process parameters and are found to be in close agreement with the theoretical predictions. Simulation results of the derived multiplier demonstrate a − 3 dB bandwidth of 9.6 MHz, a THD less than 1.21%, and an output referred noise less than 14 nV/√Hz at 1 kΩ load condition. The maximum power consumption of the circuit is 0.75 mW. The applications of the proposed multiplier as a squarer, an amplitude modulator and a frequency doubler are also included.

We propose in this paper a new MOS current-mode logic (MCML) approach for implementing ultra-rapid and accurate comparators for flash ADC applications. The speed-to-power ratio of the MCML comparator is improved by a factor of 3 compared to CMOS latch counterparts. MCML is also used to build up the subsequent 6-bit flash decoder block which exhibits better performance than the