MOS Current Mode Logic

A comprehensive study of the MOS Current Mode Logic (MCML) is presented. Operation of a conventional MCML latch is analyzed and some modified structures are described. A novel structure is proposed for increased stability with reduced delay parameters. General problems with single-ended to differential conversion are addressed. Comparative performance measures of Master-Slave (MS) latches are presented in a 0.18-µm CMOS technology.

This paper explores the resistance of MOS Current Mode Logic (MCML) against attacks based on the observation of the power consumption. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from Differential Power Analysis and similar side-channel attacks. In order to demonstrate the effectiveness of different logic styles against power analysis attacks, two full cores implementing the AES algorithm were realized and implemented with CMOS and MCML technology, and a set of different types of attack was performed using power traces derived from SPICE-level simulations. Although all keys were discovered for CMOS, MCML traces did not presents characteristic that can lead to a successful attack.

An automated optimization-based design strategy is proposed for single-level MOS Current Mode Logic (MCML) gates to overcome the complexities of the gate design procedure. The proposed design methodology determines the values of the design variables that achieve the minimum power dissipation point while attaining the required performance. The proposed design methodology has the advantage of speed, accuracy, and ability to include a large number of parameters in the design problem. Moreover, a formulation for the impact of parameter variations on the MCML gate performance is presented. The proposed strategy is used to design two popular circuits, namely; the ring oscillator and clock distribution network drivers with an average error from the required performance within 8%. The dependence of the gate parameters on parameter variations is used with the design methodology to redesign the same circuits while considering parameter variations. Furthermore, the impact of parameter variations as the technology scales down is investigated.

In this paper, the impact of the wire grid size on the power-delay-area tradeoff of VLSI digital circuits with differential routing is analyzed. To this aim, the differential MOS current-mode logic (MCML) is adopted as reference logic style, and a complete differential design flow is used. Analysis shows that the choice of the grid size in differential routing has a much stronger impact on the power-delay-area tradeoff, compared to the usual single-ended case. Hence, the grid size is an important knob that must be carefully selected when differential routing is adopted. The dependence of power, delay and area on the grid size is discussed in detail through simple models, and introducing appropriate metrics. To validate the analysis and show basic dependencies in practical circuits, 30 benchmark circuits with an in-house designed MCML cell library were synthesized and routed in 0.18 mm CMOS technology.

This work discusses the computational design of microvascular polymeric materials, which aim at mimicking the behavior found in some living organisms that contain a vascular system. The optimization of the topology of the embedded three-dimensional microvascular network is carried out by coupling a multi-objective constrained genetic algorithm with a finite-element based physics solver, the latter validated through experiments. The optimization is carried out on multiple conflicting objective functions, namely the void volume fraction left by the network, the energy required to drive the fluid through the network and the maximum temperature when the material is subjected to thermal loads. The methodology presented in this work results in a viable alternative for the multi-physics optimization of these materials for active-cooling applications.

An automated optimization-based design strategy is proposed for MOS current mode logic (MCML) circuits to overcome the complexities of the design procedure. The proposed design methodology determines the values of the design variables that achieve minimum power dissipation while attaining the required performance. Furthermore, comprehensive analytical formulations of the design parameters associated with MCML circuits are presented to provide guidelines for MCML designers. The proposed design methodology has the advantages of speed, accuracy, and ability to include a large number of parameters in the design problem. Moreover, a formulation for the impact of parameter variations on MCML operation is presented. The proposed strategy is used to design two popular circuits in a 0:18 mm CMOS technology, namely; the ring oscillator and clock distribution network drivers with an average error from the required performance within 8%. The dependence of the circuit parameters on parameter variations is used with the design methodology to redesign the same circuits while considering parameter variations. Furthermore, the impact of parameter variations as technology scales down is investigated to highlight the importance of designing for variability in future CMOS technologies.

This work discusses the computational design of microvascular polymeric materials, which aim at mimicking the behavior found in some living organisms that contain a vascular system. The optimization of the topology of the embedded three-dimensional microvascular network is carried out by coupling a multi-objective constrained genetic algorithm with a finite-element based physics solver, the latter validated through experiments. The optimization is carried out on multiple conflicting objective functions, namely the void volume fraction left by the network, the energy required to drive the fluid through the network and the maximum temperature when the material is subjected to thermal loads. The methodology presented in this work results in a viable alternative for the multi-physics optimization of these materials for active-cooling applications.

This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from DPA and similar side-channel attacks. In order to demonstrate the effectiveness of different logic styles against power analysis attacks, the non-linear bijective function of the Kasumi algorithm (known as substitution box S7) was implemented with CMOS and MCML technology, and a set of attacks was performed using power traces derived from SPICE-level simulations. Although all keys were discovered for CMOS, only very few attacks to MCML were successful.

The dual-objective optimization of an integrated water/wastewater network (IWWN) is addressed by targeting for minimum fresh water consumption at the same time with operating costs reduction. An IWWN is a recycle system composed of two oriented graphs, the first encoding the water-using units (WUs) and the second, the treatment units (TUs). Although internal recycles are forbidden ab initio for the WUs graph, external recycles from the appropriate TU to the WU whose inlet restrictions are met by the partially treated water are encouraged. The corresponding mathematical model was written. A synthetic example is proposed and analyzed under several scenarios with respect to the fresh water consumption, the magnitude of internal and treated water reuse and the investment/operating costs related to the active pipes network. A comparison is made regarding the differences in network topology and fresh water consumption implied by different points from the Pareto front (PF).

In this paper, we present three digital multiplier architectures capable of operating in the gigahertz range, based on MOS Current Mode Logic (MCML) style. A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, (3x2) counter (full adder), [4:2] compressor, and master-slave flip-flop were designed and optimized for high-speed operation. Using these gates, we propose three different 8-bit MCML binary-tree multiplier architectures and compare their performance in terms of latency, throughput (number of multiplications per second) and power consumption. According to our simulation, the fastest multiplier targeting for TSMC 0.18 µm CMOS technology attains a throughput of 4.76 GHz or 4.76 Billion multiplications per second and a latency of 3.8 ns.

In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of each gate that is part of our MCML basic library. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multi-objective optimization task. Finally, the results of postlayout simulations, using the AMS 0.35 µm technology are presented.

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In this paper, we present three digital multiplier architectures capable of operating in the gigahertz range, based on MOS Current Mode Logic (MCML) style. A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, (3x2) counter (full adder), [4:2] compressor, and ...

The dual-objective optimization of an integrated water/wastewater network (IWWN) is addressed by targeting for minimum fresh water consumption at the same time with operating costs reduction. An IWWN is a recycle system composed of two oriented graphs, the first encoding the water-using units (WUs) and the second, the treatment units (TUs). Although internal recycles are forbidden ab initio for the WUs graph, external recycles from the appropriate TU to the WU whose inlet restrictions are met by the partially treated water are encouraged. The corresponding mathematical model was written. A synthetic example is proposed and analyzed under several scenarios with respect to the fresh water consumption, the magnitude of internal and treated water reuse and the investment/operating costs related to the active pipes network. A comparison is made regarding the differences in network topology and fresh water consumption implied by different points from the Pareto front (PF).

In this article, we present a new method of realization of a four-quadrant analog multiplier using operational amplifiers (OP-AMPs) and MOSFETs. The realisation is based on the quadric nature of current of MOSFET operating in triode region. The multiplier can be derived from the proposed configuration with using either bipolar or complementary metal-oxide-semiconductor (CMOS) OP-AMPs. It can be used effectively with a wide range of supply voltages down to ± 1 V and can multiply over the full scale of the supply voltage if the OP-AMPs used are rail-to-rail low voltage OP-AMPs. The performances of the proposed multiplier are tested through PSPICE (Cadence 16.6) simulation using TSMC 0.35 µm CMOS process parameters and are found to be in close agreement with the theoretical predictions. Simulation results of the derived multiplier demonstrate a − 3 dB bandwidth of 9.6 MHz, a THD less than 1.21%, and an output referred noise less than 14 nV/√Hz at 1 kΩ load condition. The maximum power consumption of the circuit is 0.75 mW. The applications of the proposed multiplier as a squarer, an amplitude modulator and a frequency doubler are also included.

A comprehensive study of the MOS Current Mode Logic (MCML) is presented. Operation of a conventional MCML latch is analyzed and some modified structures are described. A novel structure is proposed for increased stability with reduced delay parameters. General problems with single-ended to differential conversion are addressed. Comparative performance measures of Master-Slave (MS) latches are presented in a 0.18-µm CMOS technology.

High speed and low power is the dream of circuit designers. In this paper a novel self-timed logic family is presented for high-speed self-timed pipelining applications. We developed a novel triple-rail MOS current mode logic (Tr-MCML) logic family and integrated it seamlessly with self-timed pipelines. This self-timed pipeline is designed to realize power-on-demand operations that achieve both high speed and low power, which is appropriate for the design of bus drivers, asynchronous I/Os, and infinite impulse response (IIR) filters. The ripple-carry adder is used as a testbench for verification. Simulation shows that the energy-delay product (EDP) of large digital systems can be reduced significantly.

This work discusses the computational design of microvascular polymeric materials, which aim at mimicking the behavior found in some living organisms that contain a vascular system. The optimization of the topology of the embedded three-dimensional microvascular network is carried out by coupling a multi-objective constrained genetic algorithm with a finite-element based physics solver, the latter validated through experiments. The optimization is carried out on multiple conflicting objective functions, namely the void volume fraction left by the network, the energy required to drive the fluid through the network and the maximum temperature when the material is subjected to thermal loads. The methodology presented in this work results in a viable alternative for the multi-physics optimization of these materials for active-cooling applications.

This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from DPA and similar side-channel attacks.

We propose in this paper a new MOS current-mode logic (MCML) approach for implementing ultra-rapid and accurate comparators for flash ADC applications. The speed-to-power ratio of the MCML comparator is improved by a factor of 3 compared to CMOS latch counterparts. MCML is also used to build up the subsequent 6-bit flash decoder block which exhibits better performance than the