Research Interests:
Research Interests: Embedded Systems, Energy Management, Very Large Scale Integration, System on Chip, Energy Optimization, and 9 moreEnergy Dissipation, Power Supply, Circuit Design, Dynamic Voltage and Frequency Scaling, Analog Computation, Embedded System, Continuous Optimization, Energy minimization, and Processing Element
Research Interests: Pervasive Computing, Energy Management, Soc, Optimization, System on Chip, and 16 moreFrequency, Energy Optimization, Power Supply, Decoding, Implementation, NoC, Chip, System on a Chip, Dynamic Voltage and Frequency Scaling, Network on chip, FREQUENCY ASSIGNMENT, Analog Computation, Electrical And Electronic Engineering, Network on a Chip, Low voltage, and Processing Element
A 7.5-GS/s 4.5-bit analog-to-digital converter (ADC) in 65nm CMOS is presented. A two-stage track-and-hold (TAH) with clock duty cycle control reduces bandwidth requirements on the slow TAH output to enable high sampling rates with low... more
A 7.5-GS/s 4.5-bit analog-to-digital converter (ADC) in 65nm CMOS is presented. A two-stage track-and-hold (TAH) with clock duty cycle control reduces bandwidth requirements on the slow TAH output to enable high sampling rates with low power consumption. The 7.5-GS/s flash ADC consumes 52-mW and occupies 0.01-mm2. Clock duty cycle control improves ENOB from 3.5 to 3.8 with an input sinusoid at the Nyquist frequency.
Research Interests:
In this paper, we present the design, verification, system integration and the physical realization of a fully integrated high-speed analog-digital converter (ADC) macro block with 12 bit accuracy. The entire circuit architecture is built... more
In this paper, we present the design, verification, system integration and the physical realization of a fully integrated high-speed analog-digital converter (ADC) macro block with 12 bit accuracy. The entire circuit architecture is built with a modular approach, consisting of identical units organized into an easily expandable pipeline chain. A bit-overlapping technique has been employed for digital error correction between the pipeline stages to reduce possible errors that occur during analog signal processing. The circuit has been realized using 0.18 μm digital CMOS technology. The ADC macro presented in this work is capable of operating at sampling frequencies of up to 200 MHz, and still can achieve the nominal bit-resolution that was intended for 12 bit accuracy. The maximum range of the input signal amplitude can be as high as 1.6 Vpp, with 1.8 V supply voltage. The overall power consumption is estimated as 67.5 mW at 200 MHz sampling rate. The overall silicon area of the ADC is approximately 0.25 mm2. The presented ADC architecture qualifies as a very versatile embedded macro block that can be used in deep-submicron SoC design.
Research Interests:
This work presents the design and the silicon implementation of an on-line energy optimizer unit, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing elements. The optimized... more
This work presents the design and the silicon implementation of an on-line energy optimizer unit, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing elements. The optimized voltage/frequency assignments are tailored to the instantaneous workload information and fully adaptive to variations in process and temperature. The optimizer unit has a fast response time of 50 mus, occupies a silicon area of 0.021mm2 / task and dissipates 2 mW/task
Research Interests: Pervasive Computing, Energy Management, Soc, Optimization, System on Chip, and 16 moreFrequency, Energy Optimization, Power Supply, Decoding, Implementation, NoC, Chip, System on a Chip, Dynamic Voltage and Frequency Scaling, Network on chip, FREQUENCY ASSIGNMENT, Analog Computation, Electrical And Electronic Engineering, Network on a Chip, Low voltage, and Processing Element
AbstractIn this work, MOS Current Mode Logic (MCML) is analyzed for low power, low noise, mixed signal applica-tions demanding high security such as embedded cryptographic processors and smart cards. We emphasize the possible extension... more
AbstractIn this work, MOS Current Mode Logic (MCML) is analyzed for low power, low noise, mixed signal applica-tions demanding high security such as embedded cryptographic processors and smart cards. We emphasize the possible extension of MCML gate usage ...
Research Interests:
Extending data rates to meet the I/O needs of future computing and network systems is complicated by limited channel bandwidth. While a DFE can be used to compensate channel distortion, its power dissipation reduces link energy... more
Extending data rates to meet the I/O needs of future computing and network systems is complicated by limited channel bandwidth. While a DFE can be used to compensate channel distortion, its power dissipation reduces link energy efficiency, which is vitally important in complex systems. One way of reducing DFE power consumption is to use current-integrating summers. Previously published current-integrating DFEs operating above 5 Gb/s were demonstrated on simple test chips lacking support circuitry for CDR and DFE adaptation functions. The architecture presented here includes additional data paths based on current-integrating summers to realize a fully integrated RX with CDR and continuous DFE adaptation. The design also features a digital calibration loop for setting the summer bias currents so that high performance is achieved over process variations and different data rates.
Research Interests:
This paper describes an integer-N BB-PFD DPLL architecture for wireline communication applications. The feasibility of the structure is demonstrated by implementations targeting applications in the 8-to-11 Gb/s and 17-to-20 Gb/s ranges. A... more
This paper describes an integer-N BB-PFD DPLL architecture for wireline communication applications. The feasibility of the structure is demonstrated by implementations targeting applications in the 8-to-11 Gb/s and 17-to-20 Gb/s ranges. A key challenge associated with this approach is how to achieve the proportional-path latency and gain required for overall low-noise DPLL performance. In particular, it is well-known that the strong nonlinearity introduced by the BB-PFD manifests itself as a bounded limit cycle. This results in the DPLL output jitter to increase as the proportional path latency and gain increase. To minimize the negative effect of the limit cycle, the DPLL architecture features a separate low-latency proportional path, with the BB- PFD output directly controlling the DCO. Other features include controllability of the proportional-path gain and of the BBPFD gain.
Research Interests:
This paper explores the resistance of MOS Current Mode Logic (MCML) against attacks based on the observation of the power consumption. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption... more
This paper explores the resistance of MOS Current Mode Logic (MCML) against attacks based on the observation of the power consumption. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from Differential Power Analysis and similar side-channel attacks. In order to demonstrate the effectiveness of different logic styles against power analysis attacks, two full cores implementing the AES algorithm were realized and implemented with CMOS and MCML technology, and a set of different types of attack was performed using power traces derived from SPICE-level simulations. Although all keys were discovered for CMOS, MCML traces did not presents characteristic that can lead to a successful attack.
Research Interests:
Research Interests:
Research Interests: Embedded Systems, Energy Management, Very Large Scale Integration, System on Chip, Energy Optimization, and 9 moreEnergy Dissipation, Power Supply, Circuit Design, Dynamic Voltage and Frequency Scaling, Analog Computation, Embedded System, Continuous Optimization, Energy minimization, and Processing Element
Research Interests: Pervasive Computing, Energy Management, Soc, Optimization, System on Chip, and 16 moreFrequency, Energy Optimization, Power Supply, Decoding, Implementation, NoC, Chip, System on a Chip, Dynamic Voltage and Frequency Scaling, Network on chip, FREQUENCY ASSIGNMENT, Analog Computation, Electrical And Electronic Engineering, Network on a Chip, Low voltage, and Processing Element
A 7.5-GS/s 4.5-bit analog-to-digital converter (ADC) in 65nm CMOS is presented. A two-stage track-and-hold (TAH) with clock duty cycle control reduces bandwidth requirements on the slow TAH output to enable high sampling rates with low... more
A 7.5-GS/s 4.5-bit analog-to-digital converter (ADC) in 65nm CMOS is presented. A two-stage track-and-hold (TAH) with clock duty cycle control reduces bandwidth requirements on the slow TAH output to enable high sampling rates with low power consumption. The 7.5-GS/s flash ADC consumes 52-mW and occupies 0.01-mm2. Clock duty cycle control improves ENOB from 3.5 to 3.8 with an input sinusoid at the Nyquist frequency.
Research Interests:
In this paper, we present the design, verification, system integration and the physical realization of a fully integrated high-speed analog-digital converter (ADC) macro block with 12 bit accuracy. The entire circuit architecture is built... more
In this paper, we present the design, verification, system integration and the physical realization of a fully integrated high-speed analog-digital converter (ADC) macro block with 12 bit accuracy. The entire circuit architecture is built with a modular approach, consisting of identical units organized into an easily expandable pipeline chain. A bit-overlapping technique has been employed for digital error correction between the pipeline stages to reduce possible errors that occur during analog signal processing. The circuit has been realized using 0.18 μm digital CMOS technology. The ADC macro presented in this work is capable of operating at sampling frequencies of up to 200 MHz, and still can achieve the nominal bit-resolution that was intended for 12 bit accuracy. The maximum range of the input signal amplitude can be as high as 1.6 Vpp, with 1.8 V supply voltage. The overall power consumption is estimated as 67.5 mW at 200 MHz sampling rate. The overall silicon area of the ADC is approximately 0.25 mm2. The presented ADC architecture qualifies as a very versatile embedded macro block that can be used in deep-submicron SoC design.
Research Interests:
This work presents the design and the silicon implementation of an on-line energy optimizer unit, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing elements. The optimized... more
This work presents the design and the silicon implementation of an on-line energy optimizer unit, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing elements. The optimized voltage/frequency assignments are tailored to the instantaneous workload information and fully adaptive to variations in process and temperature. The optimizer unit has a fast response time of 50 mus, occupies a silicon area of 0.021mm2 / task and dissipates 2 mW/task
Research Interests: Pervasive Computing, Energy Management, Soc, Optimization, System on Chip, and 16 moreFrequency, Energy Optimization, Power Supply, Decoding, Implementation, NoC, Chip, System on a Chip, Dynamic Voltage and Frequency Scaling, Network on chip, FREQUENCY ASSIGNMENT, Analog Computation, Electrical And Electronic Engineering, Network on a Chip, Low voltage, and Processing Element
AbstractIn this work, MOS Current Mode Logic (MCML) is analyzed for low power, low noise, mixed signal applica-tions demanding high security such as embedded cryptographic processors and smart cards. We emphasize the possible extension... more
AbstractIn this work, MOS Current Mode Logic (MCML) is analyzed for low power, low noise, mixed signal applica-tions demanding high security such as embedded cryptographic processors and smart cards. We emphasize the possible extension of MCML gate usage ...
Research Interests:
Extending data rates to meet the I/O needs of future computing and network systems is complicated by limited channel bandwidth. While a DFE can be used to compensate channel distortion, its power dissipation reduces link energy... more
Extending data rates to meet the I/O needs of future computing and network systems is complicated by limited channel bandwidth. While a DFE can be used to compensate channel distortion, its power dissipation reduces link energy efficiency, which is vitally important in complex systems. One way of reducing DFE power consumption is to use current-integrating summers. Previously published current-integrating DFEs operating above 5 Gb/s were demonstrated on simple test chips lacking support circuitry for CDR and DFE adaptation functions. The architecture presented here includes additional data paths based on current-integrating summers to realize a fully integrated RX with CDR and continuous DFE adaptation. The design also features a digital calibration loop for setting the summer bias currents so that high performance is achieved over process variations and different data rates.
Research Interests:
This paper describes an integer-N BB-PFD DPLL architecture for wireline communication applications. The feasibility of the structure is demonstrated by implementations targeting applications in the 8-to-11 Gb/s and 17-to-20 Gb/s ranges. A... more
This paper describes an integer-N BB-PFD DPLL architecture for wireline communication applications. The feasibility of the structure is demonstrated by implementations targeting applications in the 8-to-11 Gb/s and 17-to-20 Gb/s ranges. A key challenge associated with this approach is how to achieve the proportional-path latency and gain required for overall low-noise DPLL performance. In particular, it is well-known that the strong nonlinearity introduced by the BB-PFD manifests itself as a bounded limit cycle. This results in the DPLL output jitter to increase as the proportional path latency and gain increase. To minimize the negative effect of the limit cycle, the DPLL architecture features a separate low-latency proportional path, with the BB- PFD output directly controlling the DCO. Other features include controllability of the proportional-path gain and of the BBPFD gain.
Research Interests:
This paper explores the resistance of MOS Current Mode Logic (MCML) against attacks based on the observation of the power consumption. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption... more
This paper explores the resistance of MOS Current Mode Logic (MCML) against attacks based on the observation of the power consumption. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from Differential Power Analysis and similar side-channel attacks. In order to demonstrate the effectiveness of different logic styles against power analysis attacks, two full cores implementing the AES algorithm were realized and implemented with CMOS and MCML technology, and a set of different types of attack was performed using power traces derived from SPICE-level simulations. Although all keys were discovered for CMOS, MCML traces did not presents characteristic that can lead to a successful attack.