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The effect of LUT and cluster size on deep-submicron FPGA performance and density

Authors:

Elias Ahmed and

Jonathan RoseAuthors Info & Claims

FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

February 2000

Pages 3 - 12

https://doi.org/10.1145/329166.329171

Published: 01 February 2000 Publication History

Abstract

We use a fully timing-driven experimental flow [4] [15] in which a set of benchmark circuits are synthesized into different cluster-based [2] [3] [15] logic block architectures, which contain groups of LUTs and flip-flops. We look across all architectures with LUT sizes in the range of 2 inputs to 7 inputs, and cluster size from 1 to 10 LUTs. In order to judge the quality of the architecture we do both detailed circuit level design and measure the demand of routing resources for every circuit in each architecture.

These experiments have resulted in several key contributions. First, we have experimentally determined the relationship between the number of inputs required for a cluster as a function of the LUT size (K) and cluster size (N). Second, contrary to previous results, we have shown that when the cluster size is greater than four, that smaller LUTs (size 2 and 3) are almost as area efficient as 4-input LUTs, as suggested in [11]. However, our results also show that the performance of FPGAs with these small LUT sizes is significantly worse (by almost a factor of 2) than larger LUTs. Hence, as measured by area-delay product, or by performance, these would be a bad choice. Also, we have discovered that LUT sizes of 5 and 6 produce much better area results than were previously believed. Finally, our results show that a LUT size of 4 to 6 and cluster size of between 4 and 10 provides the best area-delay product for an FPGA.

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https://doi.org/10.1109/ISQED60706.2024.10528778
Kim SYou J(2024)Efficient LUT Design Methodologies of Transformation between RGB and HSV for HSV Based Image EnhancementsJournal of Electrical Engineering & Technology10.1007/s42835-024-01859-yOnline publication date: 16-Mar-2024
https://doi.org/10.1007/s42835-024-01859-y
Bailey D(2023)Field‐programmable Gate ArraysDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch2(19-44)Online publication date: 5-Sep-2023
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Index Terms

The effect of LUT and cluster size on deep-submicron FPGA performance and density
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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cover image ACM Conferences

FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

February 2000

223 pages

ISBN:1581131933

DOI:10.1145/329166

Chairmen:
Steve Trimberger
Xilinx, San Jose, CA
,
Scott Hauck
Univ. of Washington, Seattle

Copyright © 2000 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 February 2000

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FPGA00: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 10 - 11, 2000

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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https://doi.org/10.1109/ISQED60706.2024.10528778
Kim SYou J(2024)Efficient LUT Design Methodologies of Transformation between RGB and HSV for HSV Based Image EnhancementsJournal of Electrical Engineering & Technology10.1007/s42835-024-01859-yOnline publication date: 16-Mar-2024
https://doi.org/10.1007/s42835-024-01859-y
Bailey D(2023)Field‐programmable Gate ArraysDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch2(19-44)Online publication date: 5-Sep-2023
https://doi.org/10.1002/9781119819820.ch2
Véstias M(2021)Field-Programmable Gate ArrayEncyclopedia of Information Science and Technology, Fifth Edition10.4018/978-1-7998-3479-3.ch020(257-270)Online publication date: 2021
https://doi.org/10.4018/978-1-7998-3479-3.ch020
Asghar Avan Loo RKruiper TZiener D(2019)Optimizing FPGA-Based Streaming Applications for Throughput Using Pipelining2019 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT47387.2019.00065(351-354)Online publication date: Dec-2019
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Udaiyakumar RJoseph SSundararajan TVigneswaran DMaheswar RAmiri I(2018)Self Clock-Gating Scheme for Low Power Basic Logic Element ArchitectureWireless Personal Communications: An International Journal10.1007/s11277-018-5385-2102:4(3477-3488)Online publication date: 1-Oct-2018
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Bauer HHoppner SPartzsch JWalter DMayr CSchraut FEisenreich H(2017)Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)10.1109/NORCHIP.2017.8124946(1-6)Online publication date: Oct-2017
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Iqbal MParvez H(2017)Optimizing routing network of shared hardware design for multiple application circuits2017 First International Conference on Latest trends in Electrical Engineering and Computing Technologies (INTELLECT)10.1109/INTELLECT.2017.8277646(1-4)Online publication date: Nov-2017
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