threshold voltage
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A reticle is a stencil used in lithography process for forming integrated circuit (IC) on silicon substrate. It consists of a thin (100 nm) coating of masking metallic patterned (features) with critical dimension (CD) of nanometers on a thicker quartz substrate. The features can be damaged by electrostatic discharge (ESD) when exposed to the environment electrostatic charge and caused deformed IC and eventually device difunctional. Semiconductor equipment materials industry (SEMI) standard established the allowable electrostatic charge on reticle based on the characterization of ESD threshold voltage on binary reticle. However, there is another type of reticle which is phase-shift mask (PSM), has not been characterized for its ESD threshold voltage. A direct current (DC) voltage is applied directly to the structures with CD of 80 nm, 110 nm, and 160 nm. The surface current is recorded at all levels of stress from 1 to 100 V. The current–voltage (IV) curve and physical inspection results for each cell are then reviewed and classified. The results yielded which no electric field induced migration (EFM) defect and breakdown voltage occurred at any of the structures. The cathode’s metal work function has been identified as the factor that influences the PSM reticle ESD threshold voltage.

<span>This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W_F=5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.</span>

Spiking Neural Networks (SNN) are fast emerging as an alternative option to Deep Neural Networks (DNN). They are computationally more powerful and provide higher energy-efficiency than DNNs. While exciting at first glance, SNNs contain security-sensitive assets (e.g., neuron threshold voltage) and vulnerabilities (e.g., sensitivity of classification accuracy to neuron threshold voltage change) that can be exploited by the adversaries. We explore global fault injection attacks using external power supply and laser-induced local power glitches on SNN designed using common analog neurons to corrupt critical training parameters such as spike amplitude and neuron’s membrane threshold potential. We also analyze the impact of power-based attacks on the SNN for digit classification task and observe a worst-case classification accuracy degradation of −85.65%. We explore the impact of various design parameters of SNN (e.g., learning rate, spike trace decay constant, and number of neurons) and identify design choices for robust implementation of SNN. We recover classification accuracy degradation by 30–47% for a subset of power-based attacks by modifying SNN training parameters such as learning rate, trace decay constant, and neurons per layer. We also propose hardware-level defenses, e.g., a robust current driver design that is immune to power-oriented attacks, improved circuit sizing of neuron components to reduce/recover the adversarial accuracy degradation at the cost of negligible area, and 25% power overhead. We also propose a dummy neuron-based detection of voltage fault injection at ∼1% power and area overhead each.

AbstractAlthough SRAM is a well-established type of volatile memory, data remanence has been observed at low temperature even for a power-off state, and thus it is vulnerable to a physical cold boot attack. To address this, an ultra-fast data sanitization method within 5 ns is demonstrated with physics-based simulations for avoidance of the cold boot attack to SRAM. Back-bias, which can control device parameters of CMOS, such as threshold voltage and leakage current, was utilized for the ultra-fast data sanitization. It is applicable to temporary erasing with data recoverability against a low-level attack as well as permanent erasing with data irrecoverability against a high-level attack.

In this work, a hydrogen-terminated (H-terminated) diamond field effect transistor (FET) with HfAlOx/Al2O3 bilayer dielectrics is fabricated and characterized. The HfAlOx/Al2O3 bilayer dielectrics are deposited by the atomic layer deposition (ALD) technique, which can protect the H-terminated diamond two-dimensional hole gas (2DHG) channel. The device demonstrates normally-on characteristics, whose threshold voltage (VTH) is 8.3 V. The maximum drain source current density (IDSmax), transconductance (Gm), capacitance (COX) and carrier density (ρ) are −6.3 mA/mm, 0.73 mS/mm, 0.22 μF/cm2 and 1.53 × 1013 cm−2, respectively.

Liquid crystal director distributions have been numerically analyzed between asymmetric anchoring surfaces, that is, infinitely strong and very weak anchoring strength interfaces. In a hybrid aligned nematic (HAN) cell and a twisted nematic (TN) cell, HAN and TN orientations turn to a homogeneous orientation when the weak anchoring strength is lower than a critical one. Relationships between the anchoring strength and elastic constants of the liquid crystal were analyzed to be of a quasi-homogeneous orientation. The quasi-homogeneous orientation returned to the original HAN and TN orientations under voltage application. Low-driving electro-optical properties with no threshold voltage can be obtained in a quasi-homogeneous HAN cell. A unique voltage–transmission curve of 0–100–0% appeared in a quasi-homogeneous TN cell between the crossed polarizers.

Abstract Organic field effect transistors (OFETs), used in the fabrication of nano-sensors, are one of the most promising devices in the field of organic electronics, because of their light weight, flexible and low fabrication cost. However, the optimization of such OFETs is still in an early stage due to the very limited analytical as well as numerical models presented in the literature. This research presses to demonstrate a numerical carrier transport model based on finite element method (FEM), to investigate the I-V characteristic of OFETs. Two various organic semiconductor materials have been included in the study, polyaniline and pentacene, where a micro-scale as well as a nano-scale models have been presented. OFETs have been studied in terms of channel length, dielectric thickness, and doping level impact. We nominated the threshold voltage, the on/off current ratio, the sub threshold swing, and the field effect mobility’s as the main output evaluating parameters. The numerical model has shown the criticality of the doping effect on tuning the device flowing drain current, to exceed 300 μA saturation current, along with threshold voltage of -0.1 V under a channel length of 30 nm. Additionally, the study highlights the effectiveness of the polyaniline over pentacene as nano-channel length OFET, due to the boosted conductivity of polyaniline with respect to pentacene.