EE 316 / Prof.

Saraswat

Handout 5

MOS TRANSISTOR REVIEW

VG = VD = 0

VG > 0 VD = 0

VG > VT VD > 0

3D band diagram of a long channel enhancement mode NMOS transistor

EE 616 / Saraswat.

VG (+) N+ P
Inversion Layer Depletion Region

+VD (small) D
ID

N+

VD

VG(+) N+ P N+

+VD
D

ID

VD

VG N+
Inversion layer pinches off

VD = VDSAT
ID

N+

P
VD

VG N+
Inversion layer ends

VD > VDSAT N+

ID

P
2

VD

MOS Transistor

From EE216 notes: Drain current ID =

J x dydz = W QI n E x dy
Q I (y) = C [ V G V T (y)] ox

Charge density in the channel:

Gate voltage required to induce inversion under the influence of VD V T ( y) = V FB + 1 Cox 2 s q N a 2 p ( V B V ( y)) 2 p + V ( y)

Solving the above 3 equations we get I D VD characteristics Linear Region ID = W C VG VT VD L n ox

Saturation Region I DSAT

W n ox 2 L t ox

(V G

VT )

EE 616 / Saraswat.

MOS Device Scaling

N+

N+

Scaled MOS Transistor

lo
P
Why do we scale MOS transistors? 1. Increase device packing density 2. Improve frequency response (transit time) 3. Improve current drive (transconductance gm)

1 L

gm =

I D VG VD = const

K W for VD < VD SAT , linear region n ox VD L t ox K W n ox (VG VT ) for VD > VD SAT , saturation region L t ox
Decreasing the channel length and gate oxide thickness increases gm, i.e., the current drive of the transistor. Much of the scaling is therefore driven by decrease in L and tox. However if only these two parameters are scaled many problems are encountered, e.g., increased electric field. In 1974 Dennard proposed a scaling methodology which maintains the electric field in the device constant. (Dennard et al., IEEE JSSCC, 9, pp. 256-268, 1974)

Device/Circuit Parameter Constant Field Scaling Factor Dimension : xox, L, W, Xj, 1/K Substrate doping : Na K Supply voltage : Supply current : Gate Capacitance : Gate delay : Power dissipation : V I W L/xox CV/I C V2 / delay
4

1/K 1/K 1/K 1/K 1/K2

MOS Transistor

In reality constant field scaling has not been observed strictly. Since the transistor current is proportional to the gate overdrive (VG-VT), high performance demands have dictated the use of higher supply voltage. However, higher supply voltage implies increased power dissipation (CV2f). In the recent past low power applications have become important and have required a scaling scenario with lower supply voltage.

PARAMETER Channel length (m) Gate oxide (nm) Junction depth (m) Power supply voltage

1970
10

1980 4 50 0.8 5

1990 1 15 0.3 3.3 - 5

2000
0.18

2006
0.1

120 >1 12

4 0.08 1.5-1.8

1.5 0.02-0.03 0.6-0.9

Ref: Davri, et al. Proc. IEEE, April 1995

Device/Circuit Parameter Dimension : Substrate doping : Supply voltage : L, W, x ox, Xj, N V

Quasi Constant Voltage Scaling (K>B>1) 1/K K 1/B

EE 616 / Saraswat.

Limitations of Scaled MOSFET Effect of Reducing Channel Length: Drain Induced Barrier Lowering (DIBL)
In devices with long channel lengths, the gate is completely responsible for depleting the semiconductor (QB ). In very short channel devices, part of the depletion is accomplished by the drain and source bias Since less gate voltage is required to deplete QB, V T as L . Similarly, as VD , more Q B is depleted by the drain bias, and hence VT . These effects are particularly pronounced in lightly doped substrates.

Gate
Depletion region

N+ source

N+ drain

P-Si QB depleted by source QB depleted by drain

If the channel length becomes too short, the depletion region from the drain can reach the source side and reduces the barrier for electron injection. This is known as punch through.
Gate

N+ source

N+ drain

Direct carrier injection

Depletion-region boundaries

In devices with long channel lengths, the gate is completely responsible for depleting the semiconductor (QB ). In very short channel devices, part of the depletion is accomplished by the drain and source bias. Since less gate voltage is required to

MOS Transistor

deplete QB , the barrier for electron injection from source to drain decreases. This is known as drain induced barrier lowering (DIBL).

Potential variation along the channel illustrating drain induced barrier lowering (DIBL). DIBL results in an increase in drain current at a given VG . Therefore VT as L. Similarly, as VD , more QB is depleted by the drain bias, and hence ID and VT.

Effect of drain induced barrier lowering on drain current.

EE 616 / Saraswat.

V TH

VTH

VD

Carrier Mobility: Velocity Saturation The mobility of the carriers reduces at higher electric fields normally encountered in small channel length devices due to velocity saturation effects.

Velocity as a function of electric field

As the channel length, L, is reduced while the supply voltage is not, the tangential electric field will increase, and the carrier velocity may saturate. c 104 V/cm for electrons. Hence for N-channel MOSFET with L < 1 m, velocity saturation causes the channel current to reach saturation before VD = V G - VT . Instead of IDSAT being proportional (V -VT)2 it is linearly proportional to (VG -VT) and is G approximately given by

I Dsat = WC ox (VG VT )v sat

MOS Transistor

ec 5 104 V/cm for holes, hence velocity saturation for P-channel MOSFET will not become important until L < 0.25 m.

Figure. Effects of velocity saturation on the MOSFET I-V characteristics. (a)Experimental characteristics of a MOSFET with L = 2.7 m, x0 =0.05 m, Comparative theoretical characteristics computed (b) including velocity saturation and (c) ignoring velocity saturation.

Subthreshold Conduction When the surface is in weak inversion (i.e., o < s < - p, VG < VT), a conducting channel starts to form and a low level of current flows between source and drain.
ID

ID
VT

60 mv/decade

Subthreshold current Ideal

S < 60 mv/decade
VG

VT
9

V GS

EE 616 / Saraswat.

In MOS subthreshold slope S is limited to kT/q (60mV/dec)

ID leakage Static power Circuit instability

VDD is scaled for low power,delay, VT must scale to maintain ID (ON)

max =

2qN a ( i VD ) ox

In the case of MOS transistor the maximum electric field is near the drain-substrate junction. The drain reverse bias has to be dropped from drain to source. As the channel length is reduced the electric field intensity in the channel near the drain increases more rapidly in comparison to the long channel case as i does not scale.

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MOS Transistor

The free carriers passing through the high-field can gain sufficient energy to cause several hot-carrier effects. This can cause many serious problems for the device operation. Hot carriers can have sufficient energy to overcome the oxide-Si barrier. They are injected from channel to the gate oxide (process 1) and cause gate current to flow. Trapping of some of this charge can change VT permanently. Avalanching can take place producing electron-hole pairs (process 2). The holes produced by avalanching drift into the substrate and are collected by the substrate contact (process 3) causing Isub IR drop due to Isub(process 4) can cause substrate-source junction to be forward biased causing electrons to be injected from source into substrate (process 5). Some of the injected electrons are collected by the reversed biased drain and cause a parasitic bipolar action (process 5).

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EE 616 / Saraswat.

Gate Oxide Degradation and Breakdown

e Cathode
(3)

(1)

Oxide
(5) h (6)

e
(2) (3) e Hydrogen (4) h
Ref: Apte & Saraswat IEEE Trans. Electron Dev., Sept 1994

Anode

Damage cluster Anode

SiO2

Cathode Damage initiation Damage propagation Breakdown

Breakdown field ~ 8 MV/cm for thick oxides and increases > 10 MV/cm for thinner oxides.
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MOS Transistor

Band-to-Band Tunneling For small gate bias at high drain bias a significant drain leakage can be observed, especially for short channel devices.

The electric field can be very high in the drain region for VD high and VG = 0. This can cause band-to-band tunneling. This will happen only if the electric field is sufficiently high to cause large band bending.

The figure below shows band-to-band tunneling

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EE 616 / Saraswat.

Effect of Reducing Channel Width on VT There are no diffusions on the side of the channel. Hence the depletion region extends sideways in areas lying outside the gate controlled region increasing the apparent channel width. As a result the VT is increased. Note that the effect here is opposite to that of reducing channel length.

Gate

Side View of the MOS transistore

VT

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