EEE 4211 Microprocessor and I/O System

SAP-1

Introduction to SAP-1
Simple 8 bit Microprocessor 8 bit address and data bus (4 bit address and 8 bit data bus) 12 bit control bus Only 5 instructions

SAP-1 Architecture
Cp PC Ep 4 8 A La Ea

8
Eu Lm MAR 8 4 ALU Su

8 Bit Address and Data Bus

4
Lb 8 B

CE

18X8 RAM

Li Ei

4 IR 8 8 Output Register

Lo'

Controller

CpEpLmCELiEiLaEaSuEu LbLo

4
Binary Display

12

Instructions
LDA ADDR4 ADD ADDR4 SUB ADDR4 OUT HLT

Instructions
LDA
LDA ADDR4 means load the accumulator with the contents of a memory location. LDA 7h load the accumulator with the content of memory location 7. So in this case accumulator will be loaded with 10101000 (A8h)

Instructions
ADD
ADD ADDR4 means add the accumulator with the contents of a memory location. ADD 6h adds the accumulator with the content of memory location 6. So in this case The value of the accumulator will be 11001110(CEh)

A=00000010

Instructions
SUB
SUB ADDR4 means subtract the accumulator with the contents of a memory location. SUB Ah subtract the value of memory A from the accumulator. So in this case The value of the accumulator will be 00000000(00h)

A=11000101

Instructions
OUT
OUT means to place the value of the accumulator to the output register.. So, After the instruction, The out put register will contain 11000101.

A=11000101

Instructions
HLT
HLT means to suspend the execution of current instructions.

OPCODES
LDA-0000 ADD-0001 SUB-0010 OUT-1110 HLT-1111

Instruction Cycle
Two steps:
Fetch Execute

Fetch Cycle
Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC
Unless told otherwise

Instruction loaded into Instruction Register (IR)

Execution Cycle
Controller generates control signals in accordance with the instruction.

Instruction Cycle (LDA)

LDA addr4 LDA instruction is followed by a 4 bit address Suppose the instruction to be executed is LDA 5h.

Fetch Cycle (T1 State) Address State

Cp 0000 Ep 4 8 A Ea La

8
Eu Lm 0000 8 4 ALU Su

CE

.[0101]=0011100 0 . . . [0000]-0000 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 4 IR 8 8 Output Register Lo

Li Ei

Controller

Ep Lm

4
Binary Display

12

Fetch Cycle (T2 State) Increment State

Cp 0001 Ep 4 8 A Ea La

8
Eu Lm 0000 8 4 ALU Su

CE

.[0101]=0011100 0 . . . [0000]-0000 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 4 IR 8 8 Output Register Lo

Li Ei

Controller

4
Binary Display

12
Cp

Fetch Cycle (T3 State) Memory State

Cp 0001 Ep 4 8 A Ea La

8
Eu Lm 0000 8 4 ALU Su

CE

.[0101]=0011100 0 . . . [0000]-0000 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 4 0000 0101 8 8 Output Register Lo

Li Ei

Controller

Ce Li

0000 12

Binary Display

Execution Cycle (T4 State)

Cp 0001 Ep 4 8 A Ea La

8
Eu Lm 0101 8 0101 ALU Su

CE

.[0101]=0011100 0 . . . [0000]-0000 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 0101 0000 0101 8 8 Output Register Lo

Li Ei

Controller

Ei Lm

4
Binary Display

12

Execution Cycle (T5 State)

Cp 0001 Ep 4 00111000 00111000 La Ea

8
Eu Lm 0101 8 4 ALU Su

CE

.[0101]=00111000 . . . [0000]-0000 0101

8 Bit Address and Data Bus

4
Lb 8 B 00111000 4 0000 0101 8 8 Output Register Lo'

Li Ei

Controller

4
Binary Display

12
CELa

Instruction Cycle (ADD)

ADD addr4 ADD instruction is followed by a 4 bit address Suppose the instruction to be executed is ADD 5h.

Fetch Cycle (T1 State) Address State

Cp 0000 Ep 4 8 1000000 Ea La

8
Eu Lm 0000 8 4 ALU Su

CE

.[0101]=0011100 0 . . . [0000]-0001 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 4 IR 8 8 Output Register Lo

Li Ei

Controller

Ep Lm

4
Binary Display

12

Fetch Cycle (T2 State) Increment State

Cp 0001 Ep 4 8 1000000 Ea La

8
Eu Lm 0000 8 4 ALU Su

CE

.[0101]=0011100 0 . . . [0000]-0001 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 4 IR 8 8 Output Register Lo

Li Ei

Controller

4
Binary Display

12
Cp

Fetch Cycle (T3 State) Memory State

La 0001 Ep 4 8 10000000 Ea

8
Eu Lm 0000 8 4 ALU Su

CE

.[0101]=0011100 0 . . . [0000]-0001 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 4 0001 0101 8 8 Output Register Lo

Li Ei

Controller

Ce Li

0001 12

Binary Display

Execution Cycle (T4 State)

Cp 0001 Ep 4 8 10000000 Ea La

8
Eu Lm 0101 8 0101 ALU Su

CE

.[0101]=0011100 0 . . . [0000]-0001 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 0101 0001 0101 8 8 Output Register Lo

Li Ei

Controller

Ei Lm

4
Binary Display

12

Execution Cycle (T5 State)

Cp 0001 Ep 4 8 10000000 Ea La

8
Eu Lm 0101 8 4 ALU Su

CE

.[0101]=0011100 0 . . . [0000]-0001 0101

8 Bit Address and Data Bus

4
Lb 00111000 00111000 00111000 0101 0001 0101 8 8 Output Register Lo

Li Ei

Controller

Ce Lb

4
Binary Display

12

Execution Cycle (T6 State)

Cp 0001 Ep
10000 000

La 4 10111000 10111000 Ea

Eu Lm 0101 10111000
8 Bit Address and Data Bus

CE

.[0101]=0011100 0 . . . [0000]-0001 0101

00111000

Li Ei

0001 0101 8

Controller

Eu La

4 8 0101

ALU Su

Lb 8 00111000

Lo 8 Output Register

Binary Display

12

Instruction Cycle (SUB)

SUB addr4 SUB instruction is followed by a 4 bit address Suppose the instruction to be executed is SUB 4h.

Fetch Cycle (T1 State) Address State

Cp 0000 Ep 4 8 1000000 Ea
8

La

Eu Lm 0000 8
8 Bit Address and Data Bus

CE

.[0100]=0011100 0 . . . [0000]-0010 0101

Li Ei

IR 8

Controller

Ep Lm

4 8 4

ALU Su

Lb 8 B

Lo 8 Output Register

Binary Display

12

Fetch Cycle (T2 State) Increment State

Cp 0001 Ep 4 8 1000000 Ea La

8
Eu Lm 0000 8 4 ALU Su

CE

.[0100]=0011100 0 . . . [0000]-0010 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 4 IR 8 8 Output Register Lo

Li Ei

Controller

4
Binary Display

12
Cp

Fetch Cycle (T3 State) Memory State

Cp 0001 Ep 4 8 10000000 Ea La

8
Eu Lm 0000 8 4 ALU Su

CE

.[0100]=0011100 0 . . . [0000]-0010 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 4 0010 0100 8 8 Output Register Lo

Li Ei

Controller

Ce Li

0010 12

Binary Display

Execution Cycle (T4 State)

Cp 0001 Ep 4 8 10000000 Ea La

8
Eu Lm 0100 8 0100 ALU Su

CE

.[0100]=0011100 0 . . . [0000]-0001 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 0100 0010 0100 8 8 Output Register Lo

Li Ei

Controller

Ei Lm

4
Binary Display

12

Execution Cycle (T5 State)

Cp 0001 Ep 4 8 10000000 La

8
Eu Lm 0101 8 4 ALU Su

CE

.[0100]=0011100 0 . . . [0000]-0001 0101

8 Bit Address and Data Bus

4
Lb 00111000 00111000 00111000 0100 0010 0100 8 8 Output Register Lo

Li Ei

Controller

Ce Lb

4
Binary Display

12

Execution Cycle (T6 State)

Cp 0001 Ep 4 00001000 00001000 Ea La

10000 000
Eu Lm 0100 00001000 4 ALU Su

CE

.[0100]=0011100 0 . . . [0000]-0001 0101

8 Bit Address and Data Bus

00111000

4
8 8 4 0010 0100 8 8

Lb 00111000

Li Ei

Lo Output Register

Controller

Su La

4
Binary Display

12

Instruction Cycle (OUT)

OUT

Fetch Cycle (T1 State) Address State

Cp 0000 Ep 4 8 1000000 Ea La

8
Eu Lm 0000 8 4 ALU Su

CE

.[0100]=0011100 0 . . . [0000]-1110 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 4 IR 8 8 Output Register Lo

Li Ei

Controller

Ep Lm

4
Binary Display

12

Fetch Cycle (T2 State) Increment State

Cp 0001 Ep 4 8 1000000 Ea La

8
Eu Lm 0000 8 4 ALU Su

CE

.[0100]=0011100 0 . . . [0000]-1110 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 4 IR 8 8 Output Register Lo

Li Ei

Controller

4
Binary Display

12
Cp

Fetch Cycle (T3 State) Memory State

Cp 0001 Ep 4 8 10000000 Ea La

8
Eu Lm 0000 8 4 ALU Su

CE

.[0100]=0011100 0 . . . [0000]-0010 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 4 1110 0101 8 8 Output Register Lo

Li Ei

Controller

Ce Li

1110 12

Binary Display

Execution Cycle (T4 State)

Cp 0001 Ep 4 8 10000000 Ea La

8
Eu Lm 0000 8 4 ALU Su

CE

.[0100]=0011100 0 . . . [0000]-0010 0101

8 Bit Address and Data Bus

4
Lb 8 B 8 4 1110 0101 8 8 10000000 Lo

Li Ei

Controller

Ea Lo

1110 12

10000000