LF351
LF351
LF351
s LOW INPUT BIAS AND OFFSET CURRENT s OUTPUT SHORT-CIRCUIT PROTECTION s HIGH INPUT IMPEDANCE JFET INPUT
STAGE
s INTERNAL FREQUENCY COMPENSATION s LATCH UP FREE OPERATION s HIGH SLEW RATE : 16V/s (typ)
D SO8 (Plastic Micropackage)
DESCRIPTION These circuits are high speed JFET input singleoperational amplifiers incorporating well matched, high voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias and offset currents, and low offset voltage temperature coefficient. PIN CONNECTIONS (top view)
ORDER CODE
Package Part Number LF351 LF251 LF151 Temperature Range N 0C, +70 C -40C, +105C -55C, +125C D
N = Dual in Line Package (DIP) D = Small Outline Package (SO) - also available in Tape & Reel (DT)
1 2 3 4
8 7 6 5
12345678-
Offset null 1 Inverting input Non-inverting input VCCOffset null 2 Output VCC+ N.C.
March 2001
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SCHEMATIC DIAGRAM
Parameter Supply voltage - note 1) Input Voltage - note Power Dissipation Output Short-circuit Duration - note 4) Operating Free-air Temperature Range Storage Temperature Range
2) 3)
LF151
LF251
LF351
Unit V V V mW
C C
All voltage values, except differential voltage, are with respect to the zero reference level (ground) of the supply voltages where the zero reference level is the midpoint between VCC + and VCC -. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 volts, whichever is less. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded
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Min.
Typ. 3 10 5
Max. 10 13
Unit mV
Iib
Input Bias Current -note 1 Tamb = +25C Tmin Tamb Tmax Large Signal Voltage Gain (RL = 2k, Vo = 10V) Tamb = +25C Tmin Tamb Tmax Supply Voltage Rejection Ratio (RS = 10k) Tamb = +25C Tmin Tamb Tmax Supply Current, no load Tamb = +25C T min Tamb Tmax Input Common Mode Voltage Range Common Mode Rejection Ratio (R S = 10k) Tamb = +25C Tmin Tamb Tmax Output Short-circuit Current Tamb = +25C Tmin Tamb Tmax Output Voltage Swing Tamb = +25C Tmin Tamb Tmax RL RL RL RL = 2k = 10k = 2k = 10k 11 50 25 80 80
20
Avd
200 dB 86
SVR
3.4 3.4
mA V dB
70 70 10 10 10 12 10 12 12
mA 40 60 60 V 12 13.5
IOS
Vopp
SR tr K ov GBP Ri THD en m
1.
Slew Rate Vi = 10V, R L = 2k, CL = 100pF, Tamb = +25C, unity gain Rise Time Vi = 20mV, RL = 2k, CL = 100pF, Tamb = +25C, unity gain Overshoot Vi = 20mV, RL = 2k, CL = 100pF, Tamb = +25C, unity gain Gain Bandwidth Product f = 100kHz, Tamb = +25C,V in = 10mV, R L = 2k, C L = 100pF Input Resistance Total Harmonic Distortion ( f = 1kHz, Av = 20dB RL = 2k, CL = 100pF, Tamb = +25 C,Vo = 2V pp) Equivalent Input Noise Voltage RS = 100 , f = 1KHz Phase Margin
The input bias currents are junction leakage currents which approximately double for every 10C increase in the junction temperature.
LARGE SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT versus FREQUENCY
OUTPUT VOLTAGE versus ELAPSED TIME EQUIVALENT INPUT NOISE VOLTAGE versus FREQUENCY
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Millimeters Dim. Min. A a1 B b b1 D E e e3 e4 F i L Z 0.51 1.15 0.356 0.204 7.95 2.54 7.62 7.62 6.6 3.18 5.08 3.81 1.52 0.125 Typ. 3.32 1.65 0.55 0.304 10.92 9.75 0.020 0.045 0.014 0.008 0.313 Max. Min.
Inches Typ. 0.131 0.065 0.022 0.012 0.430 0.384 0.100 0.300 0.300 0260 0.200 0.150 0.060 Max.
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Millimeters Dim. Min. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 0.1 0.65 0.35 0.19 0.25 4.8 5.8 1.27 3.81 3.8 0.4 4.0 1.27 0.6 8 (max.) 0.150 0.016 Typ. Max. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 5.0 6.2 0.189 0.228 Min. 0.004 0.026 0.014 0.007 0.010
Inches Typ. Max. 0.069 0.010 0.065 0.033 0.019 0.010 0.020 0.197 0.244 0.050 0.150 0.157 0.050 0.024
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent right s of STMicroelectronics. Specifications mentioned in this publicat ion are subject to change without notice. This pub lication supersedes and replaces all information previously suppl ied. STMicroelectronics products are not authorized for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - Printed in Italy - All Righ ts Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom http://www .st.com
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