Semi Custom Vlsi Design

Semi custom VLSI design methodologies
Advanced Training Programme on
VLSI semi custom design with FPGA
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Part - 1
VLSI design - An overview
VLSI Design Cycle

System Specification Circuit Design
Architectural Design
Physical Design
Functional Design
Fabrication
Testing & Packaging Logic Design
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Design Flow
BALAJI
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VLSI design Methodologies

Full-Custom VLSI Design Semi-Custom VLSI Design
Standard cell based IC technology Structured ASIC IC technology Programmable Logic Device (PLD) IC technology
Issues in Full Custom design

Placement Routing Sizing Design Rules
Issues in Full Custom design (continued ..)

Best size, power, performance Hand design Physical design tools
Semi-Custom standard cell based IC Technology Standard Cell

A library of pre-designed cell Place and route Integrate to yield final layout
ASIC
Semi-Custom Gate Arrays Technology
Gate Arrays
Array of prefabricated gates place and route
Higher density, faster time-to-market

Does not integrate as well with full-custom
Structured
ASIC
Semi-custom Programmable Logic Device (PLD) IC Technology

(1) Field Programmable Gate Arrays (FPGA)
- Medium granularity devices
- Member of class of devices called Field Programmable Logic (FPL)
(2) Complex Programmable Logic Devices (CPLD)

- Large granularity devices
- Typically consists of 50 Simple Programmable Logic Devices (SPLD)

Full-custom Vs Semi-custom
FPGA CPLD
ASIC Design Process

Requirements Functional Design Behavioral Description
Register Transfer Level Design
RTL Simulation Validation
Logic Design
Logic Simulation
Circuit Design
Timing Simulation
Physical Design Fabrication

Design Rule Checking (DRC)
Current ASIC Design Flow

Informal Architectural Spec Functional simulation
ASICs
Fab
Synthesis/Optimization
RTL Implementation
FPGA toolflow
HDL
(VHDL / Verilog)
Synthesize
Netlist
Map Place Route
Bitstream
Hardware design is traditionally done by modeling the system in a hardware description language An FPGA compiler (synthesis tool) generates a netlist, which is then mapped to the FPGA technology, the inferred components are placed on the chip, and the connecting signals are routed through the interconnection network.
HDL Synthesis
HDL
(VHDL / Verilog)
process(clk, reset) begin if reset = 1 then output <= 0; elsif rising_edge(clk) then output <= a XOR b; end if; end process;
Synthesize
Netlist
Map Place Route

a b Register
clk
output
clear
Bitstream
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Technology Mapping
Register
HDL
(VHDL / Verilog)
a b
clk
output
clear
Synthesize
reset
Netlist
Map Place Route
Bitstream
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Place & Route

HDL
(VHDL / Verilog)
Synthesize
Netlist
Map Place Route
Bitstream
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Semi custom VLSI Design entry (part of front end design)

In semi custom VLSI design style the required logic can be described by any one, or combination of the following techniques
Schematic Entry Hardware Description Languages VHDL Verilog AHDL State machine models High level programming languages (latest trend) systemC (C++ class library with Verilog syntax) Few Other techniques
Semi custom VLSI Synthesis (or) (part of Back end Design)

In semi custom VLSI design style the required logic (which is in suitable form) can be synthesized for any one of the following devices. FPGAs
CPLDs PLD synthesis
using ASIC cell libraries

Gate Arrays
ASIC synthesis Structured ASIC synthesis
RTL is an acronym for Register Transfer Level
RTL Coding
In RTL coding the logic is realized by transferring the data between various registers , with appropriate combinational logic.
This is suitable coding style for several synthesis tools.

70% of design time at RTL in most of the digital designs
Lib file
constraints
RTL Code
Synthesis
Net List
Synthesis Flow
High-Level Synthesis
Logic Synthesis
Physical Design
Fabrication and Packaging

Basic FPGA architecture
RTL simulation (front end) Tools

Modelsim VCS Mentor Graphics Synopsys
NCSim
Max+Plus II simulator Xilinx Simulator
Cadence
Altera Xilinx
synthesis (back end) tools

DC (design compiler) PKS (physically knowledgable synthesis) Synplify Pro Xilinx Synthesis technology (XST) Altera synthesis tool LeonardoSpectrum
Synopsys Cadence Synplicity Xilinx Altera
(ASIC) (ASIC)
(FPGA)
(FPGA)
(FPGA)
Mentor Graphics (CPLD, FPGA, or ASIC )

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Semi custom VLSI design methodologies

Advanced Training Programme on

VLSI semi custom design with FPGA

VLSI design - An overview

Advanced Training Programme on

VLSI semi custom design with FPGA

VLSI Design Cycle

Testing & Packaging Logic Design

Advanced Training Programme on

VLSI semi custom design with FPGA

Advanced Training Programme on

VLSI semi custom design with FPGA

VLSI design Methodologies

Advanced Training Programme on

VLSI semi custom design with FPGA

Issues in Full Custom design

Advanced Training Programme on

VLSI semi custom design with FPGA

Issues in Full Custom design (continued ..)

Advanced Training Programme on

VLSI semi custom design with FPGA

Semi-Custom standard cell based IC Technology Standard Cell

VLSI semi custom design with FPGA

Semi-Custom Gate Arrays Technology

Higher density, faster time-to-market

VLSI semi custom design with FPGA

Semi-custom Programmable Logic Device (PLD) IC Technology

- Member of class of devices called Field Programmable Logic (FPL)

(2) Complex Programmable Logic Devices (CPLD)

- Typically consists of 50 Simple Programmable Logic Devices (SPLD)

VLSI semi custom design with FPGA

Advanced Training Programme on

VLSI semi custom design with FPGA

ASIC Design Process

Register Transfer Level Design

RTL Simulation Validation

Physical Design Fabrication

Design Rule Checking (DRC)

VLSI semi custom design with FPGA

Current ASIC Design Flow

Advanced Training Programme on

VLSI semi custom design with FPGA

Map Place Route

Advanced Training Programme on

VLSI semi custom design with FPGA

Map Place Route

reset www.unistring.com www.stringtechnologies.net

VLSI semi custom design with FPGA

Map Place Route

Place & Route

Map Place Route