74LS245
74LS245
Features
s Bi-Directional bus transceiver in a high-density 20-pin package s 3-STATE outputs drive bus lines directly s PNP inputs reduce DC loading on bus lines s Hysteresis at bus inputs improve noise margins s Typical propagation delay times, port-to-port 8 ns s Typical enable/disable times 17 ns s IOL (sink current) 24 mA s IOH (source current) 15 mA
Ordering Code:
Order Number DM74LS245WM DM74LS245SJ DM74LS245N Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Connection Diagram
Function Table
Enable G L L H
H = HIGH Level L = LOW Level X = Irrelevant
Operation
DS006413
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DM74LS245
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI HYS VOH Parameter Input Clamp Voltage Hysteresis (VT+ VT) HIGH Level Output Voltage Conditions VCC = Min, II = 18 mA VCC = Min VCC = Min, VIH = Min VIL = Max, IOH = 1 mA VCC = Min, VIL = Min VIL = Max, IOH = 3 mA VCC = Min, VIH = Min VIL = 0.5V, IOH = Max VOL LOW Level Output Voltage IOZH IOZL II IIH IIL IOS ICC Off-State Output Current, HIGH Level Voltage Applied Off-State Output Current, LOW Level Voltage Applied Input Current at Maximum Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) Outputs HIGH Outputs LOW Outputs at Hi-Z
Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, not to exceed one second duration
Min
Max 1.5
Units V V
0.2 2.7 2.4 2 IOL = 12 mA IOL = Max VO = 2.7V VO = 0.4V A or B DIR or G VI = 5.5V VI = 7V
3.4
VCC = Min VIL = Max VIH = Min VCC = Max VIL = Max VIH = Min VCC = Max
A A mA A mA mA
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DM74LS245
Switching Characteristics
VCC = 5V, TA = 25C Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ tPLH tPHL tPZL tPZH Parameter Propagation Delay Time, LOW-to-HIGH Level Output Propagation Delay Time, HIGH-to-LOW Level Output Output Enable Time to LOW Level Output Enable Time to HIGH Level Output Disable Time from LOW Level Output Disable Time from HIGH Level Propagation Delay Time, LOW-to-HIGH Level Output Propagation Delay Time, HIGH-to-LOW Level Output Output Enable Time to LOW Level Output Enable Time to HIGH Level CL = 150 pF RL = 667 CL = 5 pF RL = 667 Conditions CL = 45 pF RL = 667 Min Max 12 12 40 40 25 25 16 17 45 45 Units ns ns ns ns ns ns ns ns ns ns
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DM74LS245
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B
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DM74LS245
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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