Buk555 100a

Philips Semiconductors
Product Specification
PowerMOS transistor Logic level FET

GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope. The device is intended for use in Switched Mode Power Supplies (SMPS), motor control, welding, DC/DC and AC/DC converters, and in automotive and general purpose switching applications.
BUK555-100A/B
QUICK REFERENCE DATA

SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER BUK555 Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance; VGS = 5 V MAX. -100A 100 25 125 175 0.085 MAX. -100B 100 22 125 175 0.11 UNIT V A W C
PINNING - TO220AB
PIN 1 2 3 tab gate drain source drain DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
d
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS VGSM ID ID IDM Ptot Tstg Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction Temperature CONDITIONS RGS = 20 k tp 50 s Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 -100A 25 18 100 125 175 175 MAX. 100 100 15 20 -100B 22 15 88 UNIT V V V V A A A W C C
THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. TYP. 60 MAX. 1.2 UNIT K/W K/W
April 1993
Rev 1.100

STATIC CHARACTERISTICS
Tmb = 25 C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IDSS IGSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 1 mA VDS = 100 V; VGS = 0 V; Tj = 25 C VDS = 100 V; VGS = 0 V; Tj =125 C VGS = 10 V; VDS = 0 V VGS = 5 V; BUK555-100A BUK555-100B ID = 13 A MIN. 100 1.0 -
BUK555-100A/B
TYP. 1.5 1 0.1 10 0.075 0.09
MAX. 2.0 10 1.0 100 0.085 0.11
UNIT V V A mA nA
DYNAMIC CHARACTERISTICS
Tmb = 25 C unless otherwise specified SYMBOL gfs Ciss Coss Crss td on tr td off tf Ld Ld Ls PARAMETER Forward transconductance Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance CONDITIONS VDS = 25 V; ID = 13 A VGS = 0 V; VDS = 25 V; f = 1 MHz VDD = 30 V; ID = 3 A; VGS = 5 V; RGS = 50 ; Rgen = 50 Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad MIN. 10 TYP. 13.5 1450 280 100 25 65 135 80 3.5 4.5 7.5 MAX. 1750 350 150 40 85 180 110 UNIT S pF pF pF ns ns ns ns nH nH nH
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tmb = 25 C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS IF = 25 A ; VGS = 0 V IF = 25 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 30 V MIN. TYP. 1.3 90 0.8 MAX. 25 100 1.7 UNIT A A V ns C
AVALANCHE LIMITING VALUE

Tmb = 25 C unless otherwise specified SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 25 A ; VDD 50 V ; VGS = 5 V ; RGS = 50 MIN. TYP. MAX. 140 UNIT mJ
April 1993
Rev 1.100
BUK555-100A/B
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
10
Zth j-mb / (K/W)
BUKx55-lv
D= 0.5 0.2 0.1 0.05 0.02 0 P D tp D= tp T t 1E+01
0.1
0.01
20
40
60
80 100 Tmb / C
120
140
160
180
0.001 1E-07
T 1E-05 1E-03 t/s 1E-01
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)

ID% Normalised Current Derating
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T

ID / A 10 7 40 30 20 3 10 0 VGS / V = 4 5 BUK555-100A
120 110 100 90 80 70 60 50 40 30 20 10 0
50
20
40
60
80 100 Tmb / C
120
140
160
180
4 VDS / V
10
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V
ID / A BUK555-100A,B
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS

RDS(ON) / Ohm VGS / V = 3 3.5 BUK555-100A
1000
0.5 0.4
2.5
100
RD O S( N)
=V
/ DS
ID
A B tp = 10 us 100 us
0.3 0.2 0.1
4 4.5 5 10
10 DC 1 ms 10 ms 100 ms 1 1 10 VDS / V 100 1000
20 ID / A
40
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS
April 1993
Rev 1.100
BUK555-100A/B
50
ID / A Tj / C = 25 150
BUK555-100A
2
VGS(TO) / V max.
40
typ.
30
1 min.
20
10
0 0 2 4 VGS / V 6 8
0 -60 -20 20 60 Tj / C 100 140 180
Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj

gfs / S BUK555-100A
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
ID / A SUB-THRESHOLD CONDUCTION
20
1E-01
1E-02
15
1E-03 2% typ 98 %
10
1E-04
1E-05
0 0 20 ID / A 40
1E-06 0 0.4 0.8 1.2 VGS / V 1.6 2 2.4
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V

a Normalised RDS(ON) = f(Tj)
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS

C / pF BUK5y5-100
2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
10000
1000
Ciss
Coss 100 Crss
-60
-20
20
60 Tj / C
100
140
180
10 0 20 VDS / V 40
Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 13 A; VGS = 5 V
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
April 1993
Rev 1.100
BUK555-100A/B
12 10 8 6 4 2 0
VGS / V
BUK555-100 VDS / V =20
120 110 100 90 80 70 60 50 40 30 20 10 0
WDSS%
80
20 QG / nC
40
20
40
60
80
100 120 Tmb / C
140
160
180
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 25 A; parameter VDS
IF / A BUK555-100A
Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 25 A
50
+
40
VDD
L VDS
30
VGS
20 Tj / C = 150 10 25
-ID/100 T.U.T. R 01 shunt
0 RGS
0 0 1 VSDS / V 2
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS VDD )
April 1993
Rev 1.100

MECHANICAL DATA
Dimensions in mm Net Mass: 2 g
BUK555-100A/B
4,5 max 10,3 max

1,3
3,7 2,8
5,9 min
15,8 max
3,0 max not tinned
3,0
13,5 min
1,3 max 1 2 3 (2x)
2,54 2,54
0,9 max (3x)
0,6 2,4
Fig.17. TO220AB; pin 2 connected to mounting base.

Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for TO220 envelopes. 3. Epoxy meets UL94 V0 at 1/8".
April 1993
Rev 1.100

DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
BUK555-100A/B
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
April 1993
Rev 1.100
This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.

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Philips Semiconductors

PowerMOS transistor Logic level FET

QUICK REFERENCE DATA

PowerMOS transistor Logic level FET

TYP. 1.5 1 0.1 10 0.075 0.09

MAX. 2.0 10 1.0 100 0.085 0.11

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

AVALANCHE LIMITING VALUE

PowerMOS transistor Logic level FET

120 110 100 90 80 70 60 50 40 30 20 10 0

Normalised Power Derating

Zth j-mb / (K/W)

D= 0.5 0.2 0.1 0.05 0.02 0 P D tp D= tp T t 1E+01

T 1E-05 1E-03 t/s 1E-01

Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)

Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T

120 110 100 90 80 70 60 50 40 30 20 10 0

Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS

0.3 0.2 0.1

10 DC 1 ms 10 ms 100 ms 1 1 10 VDS / V 100 1000

Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS

PowerMOS transistor Logic level FET

0 -60 -20 20 60 Tj / C 100 140 180

Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj

1E-06 0 0.4 0.8 1.2 VGS / V 1.6 2 2.4

Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V

Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS

Coss 100 Crss

Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 13 A; VGS = 5 V

PowerMOS transistor Logic level FET

BUK555-100 VDS / V =20

120 110 100 90 80 70 60 50 40 30 20 10 0

100 120 Tmb / C

Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 25 A

-ID/100 T.U.T. R 01 shunt

Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj

PowerMOS transistor Logic level FET

4,5 max 10,3 max

3,0 max not tinned

0,9 max (3x)

Fig.17. TO220AB; pin 2 connected to mounting base.

PowerMOS transistor Logic level FET

LIFE SUPPORT APPLICATIONS

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