25L3205
25L3205
25L3205
P/N: PM1243
MX25L3205A
GENERAL DESCRIPTION
The MX25L3205A is a CMOS 33,554,432 bit serial eLiteFlashTM Memory, which is configured as 4,194,304 x 8 internally. The MX25L3205A features a serial peripheral interface and software protocol allowing operation on a simple 3- wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS# input. The MX25L3205A provide sequential read operation on whole chip. User may start to read from any byte of the array. While the end of the array is reached, the device will wrap around to the beginning of the array and continuously outputs data until CS# goes high. After program/erase command is issued, auto program/ erase algorithms which program/erase and verify the specified page locations will be executed. Program command is executed on a page (256 bytes) basis, and erase command is executed on both chip and sector (64K bytes) basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion and error flag status of a program or erase operation. To increase user's factory throughputs, a parallel mode is provided. The performance of read/program is dramatically improved than serial mode on programmer machine. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 50uA DC current. The additional 4Kb sector with 100K erase/program endurance cycles is suitable for parameter storage and replaces the EEPROM on system. The MX25L3205A utilizes MXIC's proprietary memory cell which reliably stores memory contents even after 10K program and erase cycles.
PIN CONFIGURATIONS
16-PIN SOP (300 mil)
HOLD# VCC NC PO2 PO1 PO0 CS# SO/PO7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SCLK SI PO6 PO5 PO4 PO3 GND WP#/ACC
PIN DESCRIPTION
SYMBOL CS# SI SO/PO7(1) SCLK HOLD#(2) WP#/ACC DESCRIPTION Chip Select Serial Data Input Serial Data Output or Parallel Data output/input Clock Input Hold, to pause the serial communication (HOLD# is not for parallel mode) Write Protection: connect to GND; 12V for program/erase acceleration: connect to 12V + 3.3V Power Supply Ground Parallel data output/input (PO0~PO6 can be connected to NC in serial mode) No Internal Connection
Note: 1. PO0~PO7 are not provided on 8-LAND SON package. 2. HOLD# is recommended to connect to VCC during parallel mode.
P/N: PM1243 REV. 1.2, NOV. 06, 2006
MX25L3205A
BLOCK DIAGRAM
additional 4Kb
Address Generator
X-Decoder
Memory Array
SI
Data Register Y-Decoder SRAM Buffer Sense Amplifier HV Generator SO Output Buffer
Mode Logic
State Machine
SCLK
Clock Generator
P/N: PM1243
MX25L3205A
DATA PROTECTION
The MX25L3205A are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the poweron reset and tPUW (internal timer) may protect the Flash. other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion Software Protection Mode (SPM): by using BP0-BP2 bits to set the part of Flash protected from data change. Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP2 bits and SRWD bit from data change. Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES).
Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
P/N: PM1243
MX25L3205A
Table 1. Protected Area Sizes
Status bit BP2 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 Protection Area 32Mb None Upper 64th (Sector 63) Upper 32nd (two sectors: 62 and 63) Upper sixteenth (four sectors: 60 to 63) Upper eighth (eight sectors: 56 to 63) Upper quarter (sixteen sectors: 48 to 63) Upper half (thirty-two sectors: 32 to 63) All
Note: 1. The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
P/N: PM1243
MX25L3205A
HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1.
SCLK
HOLD#
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
PROGRAM/ERASE ACCELERATION
To activate the program/erase acceleration function requires ACC pin connecting to 12V voltage (see Figure 2), and then to be followed by the normal program/erase process. By utilizing the program/erase acceleration operation, the performances are improved as shown on table of "ERASE AND PROGRAM PERFORMACE".
12V
VHH
ACC
VIL or VIH
P/N: PM1243
MX25L3205A
Table 2. COMMAND DEFINITION
COMMAND WREN (byte) (write Enable) 1st 06 Hex 2nd 3rd 4th 5th Action sets the (WEL) write enable latch bit WRDI (write disable) 04 Hex RDID (read identification) 9F Hex RDSR (read status register) 05 Hex WRSR READ (write status (read data) register) 01 Hex 03 Hex AD1 AD2 AD3 to write new n bytes values to the read out status register until CS# goes high Fast Read Parallel (fast read Mode data) 0B Hex 55 Hex AD1 AD2 AD3 x Enter and stay in Parallel Mode until power off REMS (Read Electronic Manufacturer & Device ID) 90 Hex x x ADD (1) Output the manufacturer ID and device ID
output the to read out manufacturer the status ID and 2-byte register device ID
COMMAND SE CE (byte) (Sector (Chip Erase) Erase) 1st 2nd 3rd 4th 5th Action 20 or D8 Hex AD1 AD2 AD3 60 or C7 Hex
PP DP (Page (Deep Program) Power Down) 02 Hex B9 Hex AD1 AD2 AD3
RDP RES(Read (Release Electronic from Deep ID) Power-down) AB Hex AB Hex x x x
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. (2) It is not recommended to adopt any other code which is not in the above command definition table.
P/N: PM1243
MX25L3205A
Table 3. Memory Organization
Sector 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address Range 3F0000h 3FFFFFh 3E0000h 3EFFFFh 3D0000h 3DFFFFh 3C0000h 3CFFFFh 3B0000h 3BFFFFh 3A0000h 3AFFFFh 390000h 39FFFFh 380000h 38FFFFh 370000h 37FFFFh 360000h 36FFFFh 350000h 35FFFFh 340000h 34FFFFh 330000h 33FFFFh 320000h 32FFFFh 310000h 31FFFFh 300000h 30FFFFh 2F0000h 2FFFFFh 2E0000h 2EFFFFh 2D0000h 2DFFFFh 2C0000h 2CFFFFh 2B0000h 2BFFFFh 2A0000h 2AFFFFh 290000h 29FFFFh 280000h 28FFFFh 270000h 27FFFFh 260000h 26FFFFh 250000h 25FFFFh 240000h 24FFFFh 230000h 23FFFFh 220000h 22FFFFh 210000h 21FFFFh 200000h 20FFFFh Sector 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Range 1F0000h 1FFFFFh 1E0000h 1EFFFFh 1D0000h 1DFFFFh 1C0000h 1CFFFFh 1B0000h 1BFFFFh 1A0000h 1AFFFFh 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 000000h 19FFFFh 18FFFFh 17FFFFh 16FFFFh 15FFFFh 14FFFFh 13FFFFh 12FFFFh 11FFFFh 10FFFFh 0FFFFFh 0EFFFFh 0DFFFFh 0CFFFFh 0BFFFFh 0AFFFFh 09FFFFh 08FFFFh 07FFFFh 06FFFFh 05FFFFh 04FFFFh 03FFFFh 02FFFFh 01FFFFh 00FFFFh
P/N: PM1243
MX25L3205A
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. 3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of SPI mode 0 and mode 3 is shown as Figure 3. 5. For the following instructions: RDID, RDSR, READ, FAST_READ, RES, and REMS-the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, Parallel Mode, SE, CE, PP, EN4K, EX4K, RDP and DP the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.
(SPI mode 0)
(SPI mode 3)
SCLK
SI
MSB
SO
MSB
Note: CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is supported.
P/N: PM1243
MX25L3205A
COMMAND DESCRIPTION (1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see Figure 12)
P/N: PM1243
10
MX25L3205A
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low-> sending RDSR instruction code-> Status Register data out on SO (see Figure. 15) The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)
Program/erase error bit. When the program/erase bit set to 1, there is an error occurred in last program/erase operation. The Flash may accept a new program/erase command to re-do program/erase operation.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only. bit 7 SRWD Status Register Write Protect 1= status register write disable bit 6 Program/ erase error 1=error bit 5 0 bit 4 bit 3 bit 2 BP2 BP1 BP0 the level of the level of the level of protected protected protected block block block (note 1) (note 1) (note 1) bit 1 WEL (write enable latch) bit 0 WIP (write in progress bit)
1=write enable 1=write operation 0=not write 0=not in write enable operation
P/N: PM1243
11
MX25L3205A
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP2, BP1, BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data on SI-> CS# goes high. (see Figure 16) The WRSR instruction has no effect on b6, b5, b1, b0 of the status register for. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The selftimed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at software protected mode (SPM)
P/N: PM1243
12
MX25L3205A
Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP2, BP1, BP0 and hardware protected mode by the WP# to against data modification. Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP2, BP1, BP0.
13
MX25L3205A
(9) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 20) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
P/N: PM1243
14
MX25L3205A
(12) Enter 4Kbit Mode (EN4K) and Exit 4Kbit Mode (EX4K)
Enter and Exit 4kbit mode (EN4K & EX4K) (see Figure 27 & 28) EN4K and EX4K will not be executed when the chip is in busy state. Enter 4kbit mode then the read and write command will be executed on this 4kbit. All read and write command sequence is the same as the normal array. The address of this 4k bits is: A21~A9=0 and A8~A0 customer defined. Note 1: Chip erase and WRSR will not be executed in 4kbit mode. During Enter 4Kbit Mode, the following instructions can be accepted: WREN, WRDI, RDID, RDSR, FAST_READ, READ, SE, PP, DP, RDP, RES, REMS. Note 2: Chip erase can't erase this 4kbit About the fail status: Bit6 of the status register is used to state fail status, bit6=1 means program or erase have been failed. Any new write command will clear this bit.
(14) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Powerdown mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Se-lect (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng, please use RDID instruction. Even in Deep power-down mode, the RDP, RES, and REMS are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. The sequence is shown as Figure 23,24,25. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if
P/N: PM1243
15
MX25L3205A
continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Powerdown mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode.
Table of ID Definitions: RDID Command RES Command REMS Command manufacturer ID C2 manufacturer ID C2 memory type 20 electronic ID 15 device ID 15 memory density 16
P/N: PM1243
16
MX25L3205A
POWER-ON STATE
The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the device is fully accessible for commands like write enable(WREN), page program (PP), sector erase(SE), chip erase(CE) and write status register(WRSR). If the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - tPUW after VCC reached VWI level - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of tPUW has not passed. Please refer to the figure of "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF) - At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.
P/N: PM1243
17
MX25L3205A
ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS
RATING VALUE Industrial grade 0C to 70C for Commercial grade Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential -55C to 125C -0.5V to 4.6V -0.5V to 4.6V -0.5V to 4.6V Ambient Operating Temperature -40C to 85C for NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns. 4. All input and output pins may overshoot to VCC+0.5V while VCC+0.5V is smaller than or equal to 4.6V.
20ns
0V -0.5V
4.6V 3.6V
20ns
P/N: PM1243
18
MX25L3205A
Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing referance level 0.8VCC 0.7VCC 0.3VCC 0.2VCC AC Measurement Level Output timing referance level
0.5VCC
CL
6.2K ohm
DIODES=IN3064 OR EQUIVALENT
P/N: PM1243
19
MX25L3205A
Table 5. DC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, Temperature = 0C to 70C for Commercial grade, VCC = 2.7V ~ 3.6V)
SYMBOL PARAMETER ILI ILO ISB1 ISB2 ICC1 Input Load Current Output Leakage Current VCC Standby Current Deep Power-down Current VCC Read 1 30 30 10 20 ICC2 ICC3 VCC Program Current (PP) VCC Write Status Register (WRSR) Current ICC4 ICC5 VHH VIL VIH VOL VOH VCC Sector Erase Current (SE) VCC Chip Erase Current (CE) Voltage for ACC Program Acceleration Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCC-0.2 -0.5 0.7VCC 0.3VCC VCC+0.4 0.4 V V V V IOL = 1.6mA IOH = -100uA 1 11.5 12.5 V 1 38 mA 1 38 mA Erase in Progress CS#=VCC Erase in Progress CS#=VCC VCC=2.7V~3.6V 30 mA 1 30 mA mA mA mA mA 1 10 uA 1 50 uA 1 2 uA NOTES 1 MIN. TYP MAX. 2 UNITS uA TEST CONDITIONS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VIN = VCC or GND CS# = VCC VIN = VCC or GND CS# = VCC f=50MHz (serial) f=6MHz (parallel) f=20MHz (serial) f=1.2MHz (parallel) Program in Progress CS# = VCC Program status register in progress CS#=VCC
NOTES: 1. Typical values at VCC = 3.3V, T = 25C. These currents are valid for all product versions (package and speeds). 2. Typical value is calculated by simulation.
P/N: PM1243
20
MX25L3205A
Table 6. AC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, Temperature = 0C to 70C for Commercial grade, VCC = 2.7V ~ 3.6V)
Symbol fSCLK Parameter Clock Frequency for the following instructions: Serial FAST_READ, PP, SE, BE, DP, RES,REMS, RDP WREN, WRDI, RDID, RDSR, WRSR, EN4K, EX4K Parallel fR Clock Frequency for READ instructions Serial Parallel tCLH Clock High Time Serial Parallel tCLL Clock Low Time Serial Parallel Clock Rise Time (3) (peak to peak) Serial Parallel Clock Fall Time (3) (peak to peak) Serial Parallel tCSS S Active Setup Time (relative to C) S Not Active Hold Time (relative to C) tDSU Data In Setup Time tDH Data In Hold Time S Active Hold Time (relative to C) S Not Active Setup Time (relative to C) tCSH S Deselect Time tDIS Output Disable Time tV Clock Low to Output Valid tHO Output Hold Time HOLD# Setup Time (relative to C) HOLD# Hold Time (relative to C) HOLD Setup Time (relative to C) HOLD Hold Time (relative to C) tLZ HOLD to Output Low-Z tHZ HOLD# to Output High-Z Write Protect Setup Time Write Protect Hold Time S High to Deep Power-down Mode S High to Standby Mode without Electronic Signature Read S High to Standby Mode with Electronic Signature Read Write Status SRWD, BP2, BP1, BP0 Register Cycle Time WIP, WEL Page Program Cycle Time Sector Erase Cycle Time Chip Erase Cycle Time Alt. fC Min. D.C. Typ. Max. 50 1.5 20 1.2 Unit MHz MHz MHz MHz ns ns ns ns V/ns V/ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ms ns ms s s
fRSCLK tCH(1) tCL(1) tCLCH(2) tCHCL(2) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(2) tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(2) tHLQZ(2) tWHSL(4) tSHWL(4) tDP(2) tRES1(2) tRES2(2) tW tPP tSE tCE
90 20 3 1 64
Note: 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 5. Test condition is shown as Figure 3.
P/N: PM1243
21
MX25L3205A
Table 7. Power-Up Timing and VWI Threshold
Symbol tVSL(1) tPUW(1) VWI(1) Parameter VCC(min) to S low Time delay to Write instruction Write Inhibit Voltage Min. 30 1 1.5 Max. 10 2.5 Unit us ms V
P/N: PM1243
22
MX25L3205A
Figure 8. Serial Input Timing
tSHSL CS# tCHSL SCLK tDVCH tCHDX SI MSB tCLCH LSB tCHCL tSLCH tCHSH tSHCH
SO
High-Z
tCLQV tCLQX
tCL
tSHQZ
LSB
P/N: PM1243
23
MX25L3205A
Figure 10. Hold Timing
HOLD#
Figure 11. WP# Disable Setup and Hold Timing during WRSR when SRWD=1
CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SI
01
SO
High-Z
P/N: PM1243
24
MX25L3205A
Figure 12. Write Enable (WREN) Sequence (Command 06)
SO
High-Z
SO
High-Z
9 10 11 12 13 14 15 16 17 18
28 29 30 31
Device Identification 3 2 1 0
0 15 14 13 MSB
MSB
Notes: In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec.
P/N: PM1243 REV. 1.2, NOV. 06, 2006
25
MX25L3205A
Figure 15. Read Status Register (RDSR) Sequence (Command 05)
CS# 0 SCLK command SI 05 Status Register Out High-Z SO
X 7
9 10 11 12 13 14 15
MSB
Notes: In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec.
SI
01
SO
High-Z
SI High-Z SO
03
23 22 21 MSB
0 Data Out 1
X
Data Out 2 1 0 7
MSB
Notes: In READ mode, FAST_READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec. Detail condition please reference the waveform.
P/N: PM1243
26
MX25L3205A
Figure 18. Read Data Bytes at Higher Speed (FAST_READ) Sequence (Command 0B)
SI
0B
23 22 21
SO
High-Z
SI
SO
7 MSB
Notes: In READ mode, FAST_READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec. Detail condition please reference the waveform.
P/N: PM1243
27
MX25L3205A
Figure 19. Page Program (PP) Instruction Sequence
SI
02
23 22 21 MSB
MSB
CS#
2072
2073
2074
2075
2076
2077
2
2078
1
SI
7 MSB
MSB
MSB
SI
20 or D8
23 22 MSB
P/N: PM1243
2079
REV. 1.2, NOV. 06, 2006
28
MX25L3205A
Figure 21. Chip Erase (CE) Sequence (Command 60 or C7)
CS# 0 SCLK Command SI 60 or C7 1 2 3 4 5 6 7
Stand-by Mode
Figure 23. Release from Deep Power-down and Read Electronic Signature (RES) (Command AB)
Sequence
3 Dummy Bytes
SI
AB High-Z
23 22 21 MSB
SO
7 MSB
Stand-by Mode
Notes: In READ mode, FAST_READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec. Detail condition please reference the waveform.
P/N: PM1243
29
MX25L3205A
Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB)
High-Z SO
Stand-by Mode
Figure 25. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
CS# 0 SCLK Command 2 Dummy Bytes 1 2 3 4 5 6 7 8 9 10
SI
90
15 14 13
SO
High-Z
SI
SO
7 MSB
Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first (2) In READ mode, FAST_READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec. Detail condition please reference the waveform.
P/N: PM1243
30
MX25L3205A
Figure 26. Power-up Timing
VCC VCC(max) Program, Erase and Write Commands are Ignored Chip Selection is Not Allowed VCC(min) Reset State of the Flash VWI tPUW tVSL Read Command is allowed Device is fully accessible
time
P/N: PM1243
31
MX25L3205A
Figure 27. Enter 4Kbit Mode (EN4K) Sequence (Command A5)
SO
SO
Note: Enter and Exit 4kbit mode (EN4K & EX4K) EN4K and EX4K will not be executed when the chip is in busy state. Enter 4kbit mode then the read and write command will be executed on this 4kbit. All read and write command sequence is the same as the normal array. The address of this 4k bits is: A21~A9=0 and A8~A0 customer defined. Note 1: Chip erase and WRSR will not be executed in 4kbit mode Note 2: Chip erase can't erase this 4kbit About the fail status: Bit6 of the status register is used to state fail status, bit6=1 means program or erase have been failed. Any new write command will clear this bit.
P/N: PM1243
32
MX25L3205A
Figure 29. READ ARRAY SEQUENCE (Parallel)
CS# SCLK SI PO7,PO6, PO0 CS# SCLK SI PO7,PO6, PO0 CS# SCLK SI PO7,PO6, PO0
. Byte N
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Bit1
Bit0
X .
Byte 1
Byte 2
Hi-Z
NOTES: 1. 1st Byte='03h' 2. 2nd Byte=Address 1(AD1), AD23=BIT7, AD22=BIT6, AD21=BIT5, AD20=BIT4,....AD16=BIT0. 3. 3rd Byte=Address 2(AD2), AD15=BIT7, AD14=BIT6, AD13=BIT5, AD12=BIT4,....AD8=BIT0. 4. 4th Byte=Address 3(AD3), AD7=BIT7, AD6=BIT6, ....AD0=BIT0. 5. From Byte 5, SO Would Output Array Data. 6. Under parallel mode, the fastest access clock freq. will be changed to 1.2MHz(SCLK pin clock freq.). 7. To read array in parallel mode requires a parallel mode command (55H) before the read command. Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off. 8. In READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec.
P/N: PM1243
33
MX25L3205A
Figure 30. AUTO PAGE PROGRAM TIMING SEQUENCE (Parallel)
CS# SCLK SI PO7,PO6, PO0 CS# SCLK SI PO7,PO6, PO0 CS# SCLK SI PO7,PO6, PO0
. Byte N
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Bit1
Bit0
.
Byte 1
Byte 2
Hi-Z
NOTES: 1. 1st Byte='02h' 2. 2nd Byte=Address 1(AD1), AD23=BIT7, AD22=BIT6, AD21=BIT5, AD20=BIT4,....AD16=BIT0. 3. 3rd Byte=Address 2(AD2), AD15=BIT7, AD14=BIT6, AD13=BIT5, AD12=BIT4,....AD8=BIT0. 4. 4th Byte=Address 3(AD3), AD7=BIT7, AD6=BIT6, ....AD0=BIT0. 5. 5th byte: 1st write data byte. 6. Under parallel mode, the fastest access clock freq. will be changed to 1.2MHz(SCLK pin clock freq.). 7. To program in parallel mode requires a parallel mode command (55H) before the program command. Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off.
P/N: PM1243
34
MX25L3205A
Figure 31. Read Identification (RDID) Sequence (Parallel)
9 10
NOTES: 1. Under parallel mode, the fastest access clock freg. will be changed to 1.2MHz(SCLK pin clock freg.) To read identification in parallel mode, which requires a parallel mode command (55H) before the read identification command. Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off. 2. Only 1~3 bytes would be output for manufacturer and Device ID. It's same for serial RDID mode. 3. In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec.
P/N: PM1243
35
MX25L3205A
Figure 32. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Parallel)
SI
AB
23 22 21
High-Z PO7~0
NOTES: 1. Under parallel mode, the fastest access clock freg. will be changed to 1.2MHz(SCLK pin clock freg.) To release from deep power-down mode and read ID in parallel mode, which requires a parallel mode command (55H) before the read status register command. Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off. 2. In READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec.
P/N: PM1243
36
MX25L3205A
Figure 33. READ STATUS REGISTER TIMING SEQUENCE (Parallel)
Bit7
Bit6
Bit0
..
Hi-Z
X Byte 1 Byte 2
Hi-Z
NOTES: 1. 1st Byte='05h' 2. BIT7 status register write disable signal. BIT7=1, means SR write disable. 3. BIT6=0 ==> Program/erase is correct. 4. BIT4, 3, 2 defines the level of protected block. (BIT 5 is not used) 5. BIT1 write enable latch 6. BIT0=0 ==> Device is in ready state 7. Under parallel mode, the fastest access clock freq. will be changed to 1.2MHz(SCLK pin clock freq.). To read status register in parallel mode requires a parallel mode command (55H) before the read status register command. Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off. 8. In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec.
P/N: PM1243
37
MX25L3205A
Figure 34. Read Electronic Manufacturer & Device ID (REMS) Sequence (Parallel)
SI
90 High-Z
15 14 13
PO7~0
SI
0 Manufacturer ID
PO7~0
Device ID
NOTES: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first (2) Under parallel mode, the fastest access clock freg. will be changed to 1.2MHz(SCLK pin clock freg.) To read ID in parallel mode, which requires a parallel mode command (55H) before the read ID command. Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off. (3) In READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec.
P/N: PM1243
38
MX25L3205A
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND tVR tSHSL
CS#
tCHSL tSLCH tCHSH tSHCH
SCLK
tDVCH tCHDX tCLCH LSB IN tCHCL
SI
MSB IN
SO
High Impedance
Symbol tVR
Notes 1
Min. 0.5
Max. 500000
Unit us/V
Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table.
P/N: PM1243
39
MX25L3205A
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER Chip Erase Time Chip Erase Time (with ACC=12V) Sector erase Time Sector erase Time (with ACC=12V) Additional 4Kb Erase Time Page Programming Time Page Programming Time (with ACC=12V) Erase/Program Cycle Main Array Additional 4Kb 10K 100K cycles cycles 25 3 2.4 50 12 9.6 mS mS mS Note (4) Excludes system level overhead(3) 1 0.8 3 2.4 s s Note (4) Note (4) Min. TYP. (1) 64 51 Max. (2) 128 103 UNIT s s Note (4) Comments
Note: 1. Typical program and erase time assumes the following conditions: 25C, 3.0V, and all bits are programmed by checkerboard pattern. 2. Under worst conditions of 70C and 3.0V. Maximum values are up to including 10K program/erase cycles. 3. System-level overhead is the time required to execute the command sequences for the page program command. 4. Excludes 00H programming prior to erasure. (In the pre-programming step of the embedded erase algorithm, all bits are programmed to 00H before erasure)
LATCH-UP CHARACTERISTICS
MIN. Input Voltage with respect to GND on ACC Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. -1.0V -1.0V -1.0V -100mA MAX. 12.5V 2 VCCmax VCC + 1.0V +100mA
P/N: PM1243
40
MX25L3205A
ORDERING INFORMATION
PART NO. MX25L3205AMC-20 MX25L3205AMC-20G MX25L3205AMI-20 MX25L3205AMI-20G MX25L3205AZMC-20G MX25L3205AZMI-20G ACCESS TIME(ns) 20 20 20 20 20 20 OPERATING CURRENT(mA) 30 30 30 30 30 30 STANDBY CURRENT(uA) 50 50 50 50 50 50 0~70C 0~70C -40~85C -40~85C 0~70C -40~85C 16-SOP 16-SOP 16-SOP 16-SOP 8-SON 8-SON Pb-free Pb-free Pb-free Pb-free Temperature PACKAGE Remark
P/N: PM1243
41
MX25L3205A
PART NAME DESCRIPTION
MX 25 L 3205A M C 20 G
OPTION: G: Pb-free blank: normal SPEED: 20: 50MHz, for SPI TEMPERATURE RANGE: C: Commercial (0C to 70C) I: Industrial (-40C to 85C)
TYPE: L: 3V
P/N: PM1243
42
MX25L3205A
PACKAGE INFORMATION
P/N: PM1243
43
MX25L3205A
P/N: PM1243
44
MX25L3205A
REVISION HISTORY
Revision No. 1.0 1.1 1.2 Description 1. Removed "Preliminary" title 1. Format change 1. Added statement Page P1 All P46 Date OCT/13/2005 JUN/08/2006 NOV/06/2006
P/N: PM1243
45
MX25L3205A
Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications.
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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