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Design of Phase Shifter Packaging Based On Through Glass Via (TGV) Interposer

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Xiaofeng Sun, Yu Sun, Jing Zhang, Daquan Yu, Lixi Wan


Institute of Microelectronics, Chinese Academy of Sciences
No. 3, BeiTuCheng West Road, Chaoyang district, Beijing, 100029, PR China
Email: sunxiaofeng@ime.ac.cn
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Glass has good electrical, optical and mechanical
properties as a substrate for SiP application . Through glass
via (TGV) interposer technology can avoid complex
fabrication processes and the using of expensive equipments
comparing with through silicon via(TSV). In addition, it can
lower the cost and enhance electrical performance as weil as
reliability of the electronic package. In this paper, a kind of
TGV wafer with tungsten(W) vias is introduced and its
performance is simulated. Using this kind of TGV interposer,
a one-bit MEMS switched-line phase shifer and its
package are designed.
1 HI0UHC0H
MEMS phase shifer is an ideal component in moder
communication and radar system, which has low cost, smaller
volume and low power consumption. Because of its
complexity and uniqueness, there is few notable breakthrough
in recent years in the feld of MEMS device packaging,
which therefore limits its wide usage [I].
Glass is an excellent material for packaging because of its
weil matched coeffcient of thermal expansion(CTE) to
silicon, superior electrical insulation, low dielectric constant,
high optical transparency, great hermeticity, low warping and
resistance to corosion[2]. It is suitable for optical devices,
and microwave devices and MEMS packaging. Glass
packaging is now widely studied in electrical packaging [3].
However, the glass process is not compatible with tradition al
semiconductor process, which brings diffculties to glass
three-dimensional packaging. It is diffcult to make vertical
vias through glass wafer through wet etching, dry etching or
laser drilling. Fulflling the vias with metal is also a challenge.
In this paper, a new packaging scheme of MEMS
phase shifer is introduced using our through glass via (TGV)
interposer. Compared with through silicon via (TSV)
interposer, this TGV interposer technology can avoid complex
fabrication processes and consequently it can lower the cost.
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We have fabricated 4 inch TGV wafer with about 2000
tungsten pins, which is shown in Fig.l. The wafer use
borosilicate glass as substrate and tungsten was flled in vias.
The dielectric constant is 4.6 and the loss angle tangent (tgo)
is 37x 10-
6
, which is an excellent property for device
packaging. The diameter of tungsten pin is about 100/m and
the pitch is about 400/m. The coefcient of thermal
expansion(CTE) of the glass substrate is about 3.3 1O-
6
/k
and it is matched with silicon and suitable for bonding with
silicon.
Fig.1 Photograph of TGV wafer
Z.1 bHHa0H 01LN
The performance of TGV was simulated using fnite
element fll-wave method and the simulation model is shown
in Fig.2. Two segments of CPW were connected by three
tungsten pins and the two segments of CPW are on the
diferent side of the TGV wafer.
Fig.2 TGV simulation model
The simulated results are shown in Fig.3 and Fig.4. Fig.3
shows the insertion loss and retur loss with different radius of
tungsten pins. In the simulation model only the radius changes
fom 25 to 125/m. It is observed that the insertion loss
increased with the radius, while the retur loss changes in the
opposite way.
2012 International Conference on Electronic Packaging Technology High Density Packaging
978-1-4673-1681-1112/$31.00 m012 IEEE
808

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t_1t
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=- ==- =
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(a)
(b)
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Fig.3 Simulated results of TGV with different radius: (a)
insertion loss, (b) retu loss
Fig.4 shows the insertion loss and retur loss with different
length of tungsten pins. From Fig.4 it can be seen that the
longer tungsten pins, the higher insertion loss and the lower
retur loss were obtained.
_:_11)
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m
&_1_T11
=- _ A_\_T11
_1_1!)
A_1_T11
lA\,T\1
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V
(a)
(b)
~t 7t
t
___1.mQ!l
__ttv
Fig.4 Simulated results of TGV with different length: (a)
insertion loss, (b) retur loss
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Here a one-bit RF MEMS switched-line phase shifer was
designed which employs CPW as transmission line and three
shunt capacitive-switches. The TGV wafer is used as substrate
ofRF MEMS phase shifer. The schematic is shown in Fig.5.
(a)
(b)
Fig.5 Schematic of one-bit RF MEMS switched-line phase
shifer: (a) top view, (b) back view
The phase shifer was built on the one side (top side) of
TGV wafer and the input and output pad of RF signal was
fabricated on the other side (back side) of the TGV wafer,
which is shown in Fig.5. They are connected through tungsten
pins. Also the MEMS switches are driven through tungsten
pins form back side.
The phase shifer in degree is given by:
2"
-(/2 -11) P(12 -11)
Ag
Where Ag is wavelength of RF signal, I1 and 12 are the
lengths of reference line and delay line respectively.
The RF MEMS phase shifer can be fabricated by a
multilayer UV-LIGA process. Afer the phase shifer was
fmished, it can be bonded with a silicon cap through anodic
bon ding.
2012 International Conference on Electronic Packaging Technology High Density Packaging 809
Fig.6 Packaging ofRF MEMS phase shifer
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A kind of W flled TGV wafer is introduced and its RF
performance is simulated. Based on the TGV interposer,
packaging of a one-bit RF MEMS switched-line phase shifer
is designed. It can easily realize the RF signal in and out
through the package.
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This work was fnancially supported by National S&T
Major Project with the contract NO. 2009ZX02038-003.
Daquan Yu also appreciates the support fom the 100 Talents
Program of The Chinese Academy of Sciences.
c1cIcHCcS
. Ken Gilleo, MEMS/MoMES packaging, McGraw-Hill
(New York, 2005), pp. 65-67.
2. Yu Sun, Daquan Yu, et al. "Development of Through
Glass Tungsten Via Interconnect for 3D MEMS
Packaging", 2611 1/h L/ec/oaics Packagiag
Iechao/og:oa/eeace.pp.774-776.
3. Cui, X. Y., D. Bhatt, et al. "Glass as a Substrate for High
Density Electrical Interconnect," 266 16/h L/ec/oaics
PackagiagIechao/og:oa/eeace.Vols 1-3, pp.12-17.
2012 International Conference on Electronic Packaging Technology High Density Packaging 810

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