Adder (electronics)

In electronics, an adder or summer is a digital circuit that

performs addition of numbers. In many computers and
other kinds of processors, adders are used not only in the
arithmetic logic units, but also in other parts of the processor, where they are used to calculate addresses, table
indices, increment and decrement operators, and similar
operations.

A B
Cout

Although adders can be constructed for many numerical

representations, such as binary-coded decimal or excess3, the most common adders operate on binary numbers.
In cases where twos complement or ones complement is
being used to represent negative numbers, it is trivial to
modify an adder into an addersubtractor. Other signed
number representations require a more complex adder.

1-bit
Full
Adder

Cin

S
Schematic symbol for a 1-bit full adder with Cin and Cout drawn
on sides of block to emphasize their use in a multi-bit adder

Half adder

A
B

2 Full adder
A full adder adds binary numbers and accounts for values
carried in as well as out. A one-bit full adder adds three
one-bit numbers, often written as A, B, and C ; A and
B are the operands, and C is a bit carried in from the
previous less signicant stage.[2] The full adder is usually
a component in a cascade of adders, which add 8, 16, 32,
etc. bit binary numbers. The circuit produces a two-bit
output, output carry and sum typically represented by the
signals C and S, where sum = 2 Cout + S . The
one-bit full adders truth table is:

S
C

A
B
Cin

Half adder logic diagram

S
Carry-block

Tc
The half adder adds two single binary digits A and B. It
Cout
has two outputs, sum (S) and carry (C). The carry signal
represents an overow into the next digit of a multi-digit
addition. The value of the sum is 2C + S. The simplest
half-adder design, pictured on the right, incorporates an
XOR gate for S and an AND gate for C. With the addition Full-adder logic diagram
of an OR gate to combine their carry outputs, two half
A full adder can be implemented in many dierent ways
adders can be combined to make a full adder.[1]
The half adder adds two input bits and generates a carry such as with a custom transistor-level circuit or composed
and sum, which are the two outputs of a half adder. The of other gates. One example implementation is with S =
input variables of a half adder are called the augend and A B Cin and Cout = (A B) + (Cin (A B)) .

addend bits. The output variables are the sum and carry. In this implementation, the nal OR gate before the
carry-out output may be replaced by an XOR gate withThe truth table for the half adder is:
1

MORE COMPLEX ADDERS

out altering the resulting logic. Using only two types of

gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per TCRA (n) = THA +(n1)Tc +Ts = TF A +(n1)Tc = 6D+(n1)2D
chip.
The delay from bit position 0 to the carry-out is a little
A full adder can be constructed from two half adders by dierent:
connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder,
connecting Ci to the other input and OR the two carry out- TCRA
= THA + n Tc = 3D + n 2D
[0:cout ]
puts. The critical path of a full adder runs through both
XOR-gates and ends at the sum bit s . Assumed that an The carry-in must travel through n carry-generator blocks
XOR-gate takes 3 delays to complete, the delay imposed to have an eect on the carry-out
by the critical path of a full adder is equal to
TCRA[c0 :cn ] (n) = n Tc = n 2D

TF A = 2 TXOR = 2 3D = 6D

A design with alternating carry polarities and optimized

[3]
The carry-block subcomponent consists of 2 gates and AND-OR-Invert gates can be about twice as fast.
therefore has a delay of

Tc = 2D

More complex adders

3.1

A 2 B2

A 1 B1

A 0 B0

1-bit
Full
Adder

1-bit
Full
Adder

1-bit
Full
Adder

1-bit
Full
Adder

S3

Ripple-carry adder

C4

A 3 B3

A 2 B2

A 1 B1

A 0 B0

1-bit
Full

1-bit
Full

1-bit
Full

1-bit
Full

S3

S2

S1

S0

C4 Adder C3 Adder C2 Adder C1 Adder C0

4-bit adder with logic gates shown

A 3 B3

S2

S1

p 3 g 3 C3
p 2 g 2 C2
p 1 g 1 C1
4-bit Carry Look Ahead

C0

S0
p0 g0
PG GG

4-bit adder with carry lookahead

To reduce the computation time, engineers devised faster

ways to add two binary numbers by using carry-lookahead
adders. They work by creating two signals (P and G) for
each bit position, based on whether a carry is propagated
through from a less signicant bit position (at least one
input is a '1'), generated in that bit position (both inputs
are '1'), or killed in that bit position (both inputs are '0').
In most cases, P is simply the sum output of a half adder
and G is the carry output of the same adder. After P
and G are generated the carries for every bit position are
created. Some advanced carry-lookahead architectures
are the Manchester carry chain, BrentKung adder, and
the KoggeStone adder.

It is possible to create a logical circuit using multiple full

adders to add N-bit numbers. Each full adder inputs a
Cin, which is the Cout of the previous adder. This kind
of adder is called a ripple-carry adder, since each carry
bit ripples to the next full adder. Note that the rst (and
only the rst) full adder may be replaced by a half adder
(under the assumption that Cin = 0).
Some other multi-bit adder architectures break the adder
The layout of a ripple-carry adder is simple, which al- into blocks. It is possible to vary the length of these
lows for fast design time; however, the ripple-carry adder blocks based on the propagation delay of the circuits to
is relatively slow, since each full adder must wait for the optimize computation time. These block based adders
carry bit to be calculated from the previous full adder. include the carry-skip (or carry-bypass) adder which will
The gate delay can easily be calculated by inspection of determine P and G values for each block rather than each
the full adder circuit. Each full adder requires three levels bit, and the carry select adder which pre-generates the
of logic. In a 32-bit ripple-carry adder, there are 32 full sum and carry values for either possible carry input (0 or
adders, so the critical path (worst case) delay is 2 (from 1) to the block, using multiplexers to select the appropriinput to carry in rst adder) + 31 * 3 (for carry propaga- ate result when the carry bit is known.
tion in later adders) = 95 gate delays. The general equa- Other adder designs include the carry-select adder,
tion for the worst-case delay for a n-bit carry-ripple adder conditional sum adder, carry-skip adder, and carrycomplete adder.
is

3.2

5 References

Lookahead carry unit

[1] Georey A. Lancaster (2004). Excel HSC Software Design and Development. Pascal Press. p. 180. ISBN
9781741251753.

A48..63 B48..63 A32..47 B32..47 A16.31 B16..31 A0..15 B0..15

16-bit
LCU
Adder
S48..63
C64

16-bit
LCU
Adder
S32..47

16-bit
LCU
Adder
S16..31

16-bit
LCU
Adder

C0

S0..15

p48 g48 C48 p32 g32 C32 p16 g16 C16 p0 g0

64-bit Lookahead Carry Unit
PG GG

A 64-bit adder

[2] M. Morris Mano, Digital Logic and Computer Design,

Prentice-Hall 1979, 0-13-214510-3 pp.119-123
[3] Burgess, N. (2011).
Fast Ripple-Carry Adders in
Standard-Cell CMOS VLSI (PDF). 20th IEEE Symposium
on Computer Arithmetic. pp. 103111.

6 External links

By combining multiple carry lookahead adders even

larger adders can be created. This can be used at multiple
levels to make even larger adders. For example, the following adder is a 64-bit adder that uses four 16-bit CLAs
with two levels of LCUs.

Binary adder with visual results, A tool which visually explains how to add two binary numbers submitted by user. Helpful for beginners.

3.3

8-bit Full Adder and Subtractor, a demonstration of

an interactive Full Adder built in JavaScript solely
for learning purposes.

Carry-save adders

Main article: Carry-save adder

If an adding circuit is to compute the sum of three or more
numbers it can be advantageous to not propagate the carry
result. Instead, three input adders are used, generating
two results: a sum and a carry. The sum and the carry may
be fed into two inputs of the subsequent 3-number adder
without having to wait for propagation of a carry signal.
After all stages of addition, however, a conventional adder
(such as the ripple carry or the lookahead) must be used
to combine the nal sum and carry results.

3:2 compressors

We can view a full adder as a 3:2 lossy compressor: it

sums three one-bit inputs, and returns the result as a single
two-bit number; that is, it maps 8 input values to 4 output
values. Thus, for example, a binary input of 101 results
in an output of 1+0+1=10 (decimal number '2'). The
carry-out represents bit one of the result, while the sum
represents bit zero. Likewise, a half adder can be used as
a 2:2 lossy compressor, compressing four possible inputs
into three possible outputs.
Such compressors can be used to speed up the summation of three or more addends. If the addends are exactly three, the layout is known as the carry-save adder.
If the addends are four or more, more than one layer of
compressors is necessary and there are various possible
design for the circuit: the most common are Dadda and
Wallace trees. This kind of circuit is most notably used
in multipliers, which is why these circuits are also known
as Dadda and Wallace multipliers.

Hardware algorithms for arithmetic modules, includes description of several adder layouts with gures.

Interactive Full Adder Simulation, Interactive Full

Adder circuit constructed with Teahlabs online circuit simulator.
Interactive Half Adder Simulation, Half Adder circuit built with Teahlabs circuit simulator.
4-bit Full Adder Simulation built in Verilog, and the
accompanying Ripple Carry Full Adder Video Tutorial

7 TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES

Text and image sources, contributors, and licenses

7.1

Text

Adder (electronics) Source: https://en.wikipedia.org/wiki/Adder_(electronics)?oldid=664843556 Contributors: Timo Honkasalo, Stevertigo, Edward, Julesd, Glenn, Mrand, Ckape, Robbot, Fredrik, DavidCary, Utcursch, Vindicator, OldZeb, BioPizza, DragonySixtyseven,
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7.2

Images

File:1-bit_full-adder.svg Source: https://upload.wikimedia.org/wikipedia/commons/4/48/1-bit_full-adder.svg License: CC-BY-SA-3.0

Contributors: This vector image was created with Inkscape. Original artist: en:User:Cburnett
File:4-bit_carry_lookahead_adder.svg Source: https://upload.wikimedia.org/wikipedia/commons/0/04/4-bit_carry_lookahead_adder.
svg License: CC-BY-SA-3.0 Contributors: This vector image was created with Inkscape. Original artist: en:User:Cburnett
File:4-bit_ripple_carry_adder.svg Source: https://upload.wikimedia.org/wikipedia/commons/5/5d/4-bit_ripple_carry_adder.svg License: CC-BY-SA-3.0 Contributors: This vector image was created with Inkscape. Original artist: en:User:Cburnett
File:64-bit_lookahead_carry_unit.svg Source: https://upload.wikimedia.org/wikipedia/commons/5/58/64-bit_lookahead_carry_unit.
svg License: CC-BY-SA-3.0 Contributors: This vector image was created with Inkscape. Original artist: en:User:Cburnett
File:Half_Adder.svg Source: https://upload.wikimedia.org/wikipedia/commons/d/d9/Half_Adder.svg License: Public domain Contributors: Own drawing, Inkscape 0.43 Original artist: inductiveload
File:_Full-adder_logic_diagram.svg Source: https://upload.wikimedia.org/wikipedia/commons/6/69/Full-adder_logic_diagram.svg License: Public domain Contributors: Own drawing, Inkscape 0.43 Original artist: inductiveload

7.3

Content license

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