Basic VLSI Slides

9/5/2015
VLSIDesign
ShailendraKumarTiwari
AssistantProfessor
(SeniorScale)
Lecture01
1. Reference Books
2. Syllabus.
3. What is there for me?
4. What is expected ?
5. Are we meeting with
expectation?
6. Device generations
7. Design abstraction level
8. Moores law
9. Technology generation
10.Conclusion
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ReferenceBooks
Basic VLSI Design, 3rd Ed., PHI

By: PUCKNELL DOUGLAS A.
KAMRAN ESHRAGHIAN,
9/5/2015
CMOS DIGITAL INTEGRATED

CIRCUITS:Analysis and Design
3rd Ed. McGraw-Hill.
By:SUNG-MO (STEVE) KANG
S.K.Tiwari(Asst.Prof.ECEMITManipal)
ReferenceBooks
CMOS LOGIC CIRCUIT DESIGN

Digital Integrated Circuits A Design
KLUWER ACADEMIC PUBLISHERS
Perspective,
By: John P. Uyemura
2nd ed. by J. Rabaey, A. Chandrakasan, B.
Nikolic
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ReferenceBooks
CMOS VLSI Design:A Circuits and Systems

Perspective 4th ed. Addison-Wesley
By: Neil H. E. Weste, David Money Harris
9/5/2015
Syllabus
Course Plan
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Whatisthereforme?
http://www.pcb007.com/pages/zone.cgi?a=87231
Whatisthereforme?
http://www.pcb007.com/pages/zone.cgi?a=87231
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Whatisexpected?
1980s
1990s
2000s
Whatisexpected?
Complexity
Delay
Power
Cost
Min
Min
Min
Min
Design Time
Size
Min
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Arewemeetingwithexpectation?
W=0.7, L=0.7, Tox=0.7
Lateral and vertical
dimensions reduce 30 %
.
.
Area Cap = C =
0.7
.
Capacitance reduces by 30 %
0.7
Die Area =
0.7
0.5
Die area reduces by 50 %

Drain Current reduces by 30 %
Delay
Delay reduces by 30 %
Power
P
power reduces by 50 %
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Devicegenerations
Vacuum Tubes
BJT
FET
MOSFET
CMOS
Designabstractionlevel
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Mooreslaw
As predicted by Gordon Moore
in the 1960s, integrated circuit
(IC)
densities
have
been
doubling approximately every 18
months, and this doubling in size
has been accompanied by a
similar exponential increase in
circuit speed (or more precisely,
clock frequency)
January 3, 1929
TechnologyGeneration
Integrationlevel
Year
No.oftransistors
DRAMIntegration
SSI
1950s
Lessthan102
MSI
1960s
102 103
LSI
1970s
103 105
4K,16K,64K
VLSI
1980s
105 107
256K,1M,4M
ULSI
SLSI
1990s
2000s
107 109
Over109
16M,64M,256M
1G,4GandAbove
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MicroelectronicsTechnology
NMOS
MOS
Silicon
PMOS
CMOS
TTL
Active
Substrate
Bipolar
ECL
Micro
GaAs
Electronics
Inert
Substrate
VeryFast
Devices
Good
resistors
MOSVs.Bipolar
Factors
StaticPower
Dissipation
Input
Impedance
NoiseMargin
PackingDensity
Fanout
Direction
CMOS
Low
Bipolar
High
High
Low
High
High
Low
Bidirectional
Low
Low
High
Unidirectional
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DelayandPowerDissipationPerGate
MOSCapacitor
i. Accumulation
ii. Depletion
iii. inversion
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MOSCapacitor
NChannelMOSFET
Metal
Oxide
PSubstrate
PSubstrate
Metal
Oxide
Oxide
N+
PSubstrate
N+
PSubstrate
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NChannelMOSFET
Gate
Source
Drain
PChannelMOSFET
Metal
Oxide
NSubstrate
NSubstrate
Metal
Oxide
Oxide
P+
NSubstrate
P+
NSubstrate
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MOSFETSchematicSymbol
OperationOfNMOSTransistor
Depending on the relative voltages of the source,
drain and gate, the NMOS transistor may operate
in any of three regions viz :
Cut_off : Current flow is essentially zero (also
called accumulation region)
Linear : (Non saturated region)-It is weak
inversion region drain current depends on gate
and drain voltage.
Saturation : It is strong inversion region where
drain current is independent of drain-source
voltage.
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CutoffRegion
VGS=0
Source (S)
VDS=0
n+
n+
n+
n+
p-type substrate
(Body)
With zero gate bias (VGS=0) , no current flows between source

and drain, only the source to drain leakage current exists.
Current-voltage relation : IDS = 0
VGS < VT
LinearRegion
Formation of Depletion layer
Source (S)
0 VGS Vt
VDS=0
Depletion Layer
n+
n+
n+
n+
p-type substrate
(Body)
Small positive voltage applied to gate causes electric field to be

produced across the substrate
This in turn causes holes in P region to be repelled. This forms
the depletion layer under the gate.
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LinearRegion
Formation of Inversion layer :
Source (S)
VDS=0
VGS > Vt
Inversion Layer
n+
n+
n+
n+
p-type substrate
(Body)
the gate voltage is further increased, at particular voltage VT,

electrons are attracted to the region of substrate under gate thus forming
conduction path between source and drain.
This induced layer is called inversion layer. The gate voltage necessary
to form this layer is known as Threshold voltage (VT).
As application of electric field at gate causes formation of inversion
layer, the junction is known as field induced junction.
As
LinearRegion
Source (S)
VGS > Vt
VDS < VGS - Vt

Inversion Layer
n+
n+
n+
n+
p-type substrate
(Body)
When VDS is applied, the horizontal component of electric field (due

to source-drain voltage) and vertical component (due to gatesubstrate voltage) interact, causing conduction to occur along the
channel.
When effective gate voltage (VGS - VT) is greater than drain
voltage, current through the channel increases. This is non
saturated mode. ID = f (VGS,VDS)
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Saturation
Source (S)
VGS > Vt
n- channel
n+
n+
VDS = VGS - Vt
n+
n+
p-type substrate
(Body)
As VDS is increased, the induced Channel acquires a tapered shape and

its resistance increases with Increase in VDS.
Here VGS is kept constant at value > VT
Saturation
Source (S)
VGS > Vt
n- channel
n+
n+
VDS > VGS - Vt
n+
n+
p-type substrate
(Body)
When VDS > VGS VT, VGD < VT, the channel becomes pinched- off &
transistor is said to be in saturation.
Conduction is brought by drift mechanism of electrons under the
influence of positive drain voltage and effective channel length is
modulated.
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DepletionTypeMOS
D
Drain
Gate
Gate
Drain
Source
Source
NMOS
PMOS
NMOS
In Depletion MOS structure, the source & drain are diffused on
P- substrate as shown above.
Positive voltages enhances number of electrons from source to
drain.
Negative voltage applied to gate reduces the drain current
This is called as normally ON MOS.
DepletionTypeNMOS
Source (S)
Gate (G)
Drain (D)
Metal
Oxide (SiO2)
n+
n+
L
p-type substrate
(Body)
Body (B)
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DraintoSourceCurrentIDS
the gate and the channel region form a parallel plate

capacitor for which the oxide layer serves as a dielectric.
consider the infinitesimal strip of the gate at distance x

fromthe source. The capacitance of this strip is
CoxWdx
To find the charge stored on this infinitesimal strip of the
gate capacitance, we multiply the capacitance by the
effective voltage between the gate and the channel at
point x,
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Charge dq in the infinitesimal portion of the channel at

point x is
Negative sign accounts for the fact that dq is a negative

charge
The voltage VDS produces an electric field along the
channel in the negative x direction
The electric field E(x) causes the electron charge dq to

drift toward the drain with a velocity
Where n is the mobility of electrons in the channel (called

surface mobility).
The resulting drift current i
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Thus i must be equal to the source-to-drain current.

Since we are interested in the drain-to-source current iD,
we can find it as
Integrating both sides of this equation from x = 0 to x = L

and, correspondingly, for V(0) = 0 to V(L) = VDS,
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Current is flow of charges.
IDS=f(VGS,VDS)

Continued ..
Velocity v is given by
= electron or hole mobility (surface)

EDS= Drain to Source Electric Field
Continued ..
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n = 650 cm2/V Sec

p = 240 cm2/V Sec
The Non-Saturated Region

Charge induced in channel due to VGS.
Voltage along the channel varies linearly with distance X
from source due to IR drop in the channel.
The average value of IR drop in the channel
2
Continued ..
The effective gate voltage
VG= VGS-VT
Charge/unit area= EGins0
Charge induced in channel = WLEGins0
EG= Average electric field gate to channel.
0= 8.8510-14F/cm(Permittivity of free space)
ins= 04.0
2
D= Thickness of oxide layer
Continued ..
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2
Continued ..
Continued ..
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SaturationRegion
DraincurveforNMOSoperatedwith
VGS>VT
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IDVDScharacteristics
IVcharacteristicsofNMOS
Transconductance curve
IGS = 0
+
-
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IS = ID
+
-
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Determine the Region of Operation of M1

1
Off because VGS=0V
Non-Saturation VGS Vt =(1-0.4)V=0.6V

VDS =0V; (VGS Vt)> VDS
4
Saturation VGS Vt =(1-0.4)V=0.6V

VDS =1.5V; (VGS Vt)< VDS
Non-Saturation VGS Vt =(1.5-.4)V=1.1V

VDS =0.5V; (VGS Vt)> VDS
Non-Saturation VGS Vt =(1.5-0.4)V=1.1V

VDS =0.5V; (VGS Vt)> VDS
Saturation VGS Vt =(0.5-0.4)V=0.1V

VDS =0.5V; (VGS Vt)< VDS
7
Cut-Off VGS =0V

Saturation VGS Vt =(1-0.4)V=0.6V
VDS =1V; (VGS Vt)< VDS
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A 0.18-m fabrication process is specified to have

tox= 4nm, n=450cm2/Vs and VT=0.5V. Find the
value of nCox(Also known as kn
process
transconductance) For a MOSFET with minimum
length fabricated in this process, find the required
value of W so that the device exhibits a channel
resistance rDS of 1K at VGS=1V. Device is operating
in deep linear region.
Kn= 388A/V2
W= 0.93m
Consider a process technology for which Lmin = 0.4 m,

tox = 8 nm, n = 450 cm2/V s, and Vt = 0.7 V.
(a) Find Cox and Kn.
Cox =4.31x10-3F/m2
Kn= 194.1 A/V2
(b) For a MOSFET with W/L= 8 m 0.8 m calculate the

values of VOV, VGS, and VDSmin needed to operate the
transistor in the saturation region with a dc current
ID = 100 A. VDSmin = VOV = 0.32 V VGS = 1.015 V
(c) For the device in (b), find the values of VOV and VGS
required to cause the device to operate as a 1000-resistor
for very small vD VOV = 0.51 V VGS = 1.215 V
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For a 0.8-m process technology for which tox = 15 nm and

n = 550 cm2/Vs, find Cox, Kn , and the overdrive voltage VOV
required to operate a transistor having W/L=20 in saturation
with ID = 0.2 mA. What is the minimum value of VDS needed?
Cox =2.301x10-3F/m2 Kn= 126.5A/V2 VDSmin = VOV = .397 V0.4V
A circuit designer intending to operate a MOSFET in

saturation is considering the effect of changing the device
dimensions and operating voltages on the drain current ID.
Specifically, by what factor does ID change in each of the
following cases?
(a) The channel length is doubled.
(b) The channel width is doubled.
(c) The overdrive voltage is doubled.
(d) The drain-to-source voltage is doubled.
An enhancement type NMOS transistor with Vt = 0.7V

has its source terminal grounded and a 1.5-V DC is
applied to the gate. In what region does the device
operate :for (a) VD = +0.5 V (b) VD = +0.9 V (c) VD = +3 V
If the NMOS device in nCox = 100 A/V2 , W = 10 m,
and L = 1 m, find the value of drain current that results
in each of the three cases (a), (b), and (c).
(a) Non Satn275 A
(b) Satn320 A
(c) Satn320 A
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The PMOS transistor shown in Fig. has Vtp=-1V,

(a) Find the range of VG for which the transistor conducts.
(b) In terms of VG, find the range of VD for which the transistor
operates in the triode region.
(c) In terms of VG, find the range of VD for which the transistor
operates in saturation.
SecondorderEffects
BodyEffect.
Subthresholdconduction
Channellengthmodulation
Mobilityvariation
FowlerNordheim tunneling
Drainpunchthrough
ImpactIonizationHotelectrons.
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BodyEffect
What happens if the bulk voltage of an N-MOSFET drops
below the source voltage ?
2
where MS is the difference between the
work functions of the polysilicon gate and
the silicon substrate
F= Fermi potential
Subthresholdconduction
For VGS VTH, a "weak inversion layer still exists and
some current flows from D to S. Even for VGS < VTH, ID is
finite, but it exhibits an exponential dependence on VGS
Called "subthreshold conduction. this effect can be
formulated for VDS greater than roughly 200 m V as
>1 is a nonideality factor
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Channellengthmodulation
is a process-technology parameter
with the dimensions of V-1
VA is a process-technology
dimensions of V.
parameter
with
the
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Mobilityvariation
Mobility is the defined as the ease with which the charge
carriers drift in the substrate material. Mobility decreases
with increase in doping concentration and increase in
temperature. Mobility is the ratio of average carrier drift
velocity and electric field. Mobility is represented by the
symbol .
FowlerNordhiem tunneling:
When the gate oxide is very thin there can be a current
between gate and source or drain by electron tunneling
through the gate oxide. This current is proportional to the
area of the gate of the transistor.
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Drainpunchthrough
When the drain is a high voltage, the depletion region
around the drain may extend to the source, causing the
current to flow even it gate voltage is zero. This is known
as Punchthrough condition.
ImpactIonizationHotelectrons
When the length of the transistor is reduced, the electric field
at the drain increases. The field can be come so high that
electrons are imparted with enough energy we can term them
as hot. These hot electrons impact the drain, dislodging holes
that are then swept toward the negatively charged substrate
and appear as a substrate current. This effect is known as
Impact Ionization.
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PassTransistors(NMOS)
NMOS
NMOSPasstransistorpassesstronglogic0.
NMOSPasstransistorpassesweaklogic1.
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PassTransistors(PMOS)
PassTransistors(PMOS)
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PMOS
PMOSPasstransistorpassesweaklogic0.
PMOSPasstransistorpassesstronglogic1.
TransmissionGate
PMOS Pass transistor passes strong logic 1.

NMOS Pass transistor passes strong logic 0.
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Inverters
Inverters
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Inverters
VOH:
VOL:
VIL:
VIH:
Maximum output voltage when the output level is logic " 1

Minimum output voltage when the output level is logic 0
Maximum input voltage which can be interpreted as logic "0"
Minimum input voltage which can be interpreted as logic "1"
ResistiveLoadInverter
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EnhancementloadNMOSinverter
DepletionLoadNMOSInverter
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Calculation of VOH
When the input voltage Vin is smaller than the driver
threshold voltage VT0, the driver transistor is turned off
and does not conduct any drain current. Consequently,
the load device, which operates in the linear region, also
has zero drain current.
Substituting VOH for Vout
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Calculation of VOL
We assume that the input voltage Vin of the inverter is equal to VOH = VDD
Driver transistor linear region
Depletion-type load saturation region
This second-order equation in VOL can be solved by temporarily

neglecting the dependence of VT load on VOL, as follows.
Calculation of VIL
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Calculation of VIL
Calculation of VIH
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Calculation of VIH
Where
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CMOSInverter
VOH: Maximum output voltage when the output level is logic " 1"
VOL : Minimum output voltage when the output level is logic "0"
VIL: Maximum input voltage which can be interpreted as logic "0"
VIH: Minimum input voltage which can be interpreted as logic " 1"
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RegionA
PMOS Nonsaturation Region
NMOS Cutoff
Vout= VDD - IDRCPMOS
Vout= VDD
RegionBVIL
PMOS Nonsaturation Region
NMOS Saturation Region
The slope of the VTC is equal to
(-1), when the input voltage is V =
VIL.
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To satisfy the derivative condition at VIL we differentiate

both sides with respect to Vin.
Where
RegionCVth
PMOS Saturation Region
NMOS Saturation Region
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Where
RegionDVIH
PMOS Saturation Region
NMOS Non-saturation Region
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Where
RegionEVOL
when the input voltage exceeds VDD the pMOS transistor
is turned off. In this case, the nMOS transistor is
operating in the linear region, but its drain to- source
voltage is equal to zero because
The output voltage of the circuit
is
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MOSTransistorTransconductance gm
andoutputconductancegds
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MOSTransistorFigureofMerit
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Determination of pullup to pulldown ratio (Zp.U/

Zp.D.) For An Nmos Inverter Driven By Another Nmos
Inverter
Vinv=0.5VDD
Note
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substitute typical values as follows
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PulluptopulldownratioforanNmos inverterdriven
throughoneormorepasstransistors
Vtp = threshold voltage for a pass transistor
Now, for depletion mode p.u. in saturation with VGS = 0
Note
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Consider inverter 2 (Figure 2.10(b)) when input = VDD- Vtp.
This image cannot currently be display ed.
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Taking typical values
0.5
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Mask
Common material used for masks are Photoresist, Polysilicon,

Silicon dioxide, Silicon nitride.
To create mask:
(a) deposit mask material over entire surface
(b) cut windows in the mask to create exposed areas
(c) deposit dopant
(d) remove un-required mask material
Masks plays important role in process called selective
diffusions.
The selective diffusion involves
1. Patterning windows in a mask material on the surface of
the wafer.
2. Subjecting the exposed areas to a dopant source.
3. Removing any un-required mask material.
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Photolithography
The Process of using an optical image and a photosensitive
film to produce a pattern on a substrate is photolithography
Photolithography depends on a photosensitive film called a
photo-resist.
Types of resist
Positive resist, a resist that become soluble when exposed
and forms a positive image of the plate.
Negative resist, a resist that lose solubility when
illuminated forms a negative image of the plate.
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Photolithography
ptype body
Substrate
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Photolithography
ptype body
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Resistapplication
116
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Photolithography
ptype body
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Exposure
117
Photolithography
Etching
ptype body
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PositiveResist
118
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Photolithography
Etching
ptype body
NegativeResist
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NMOS Fabrication Steps

1. Selection of Substrate
Si(100)
PType
2. Cleaning
3. Oxidation
SiO2
Si(100)
PType
Si+O2SiO2(good quality)
Si+2H2OSiO2+ 2H2(poor quality)
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120
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4.Lithography with MASK1
UV
+VEPhotoresist
SiO2
Si(100)
PType
A
MASK1
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121
Photoresist development and Oxide Etching
Si(100)
PType
Photoresist Etching
Si(100)
PType
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122
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Gate Oxidation
Si(100)
PType
Poly Silicon Deposition
Si(100)
PType
SiH4Si+2H2
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123
UV
Lithography for Gate Electrode
+VEPhotoresist
PolySi
Si(100)
PType
MASK2
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124
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Poly Patterning
Si(100)
PType
Photoresist Cleaning
Si(100)
PType
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125
Lithography for Source and Drain region

UV
Si(100)
PType
D
MASK3
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126
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Oxide etching (HF Cleaning)
Si(100)
PType
Photoresist cleaning
Si(100)
PType
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127
5,17,21,28,30,34,43,44,51,54,55,58,
Ion Implantation
N+
Si(100)
PType
N+
Thick Oxide Deposition
N+
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Si(100)
PType
N+
128
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Lithography and Contact Opening

UV
N+
Si(100)
PType
N+
D
MASK4
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Metallization and Patterning

S
N+
Si(100)
PType
129
N+
Body terminal is not shown..
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130
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FabricationofCMOSDevices
Technologies used for CMOS fabrications include
N-well process
P-well process
Twin-tub process
Silicon on insulator.
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PWellsandNWells
In order to have both types of transistors on the same substrate, the
substrate is divided into well regions (Shaded region in the
standard cells)
Two types of wells are available - n- well and p- well
In a p- substrate, an n- well is used to create a local region of n type
substrate, wherein the designer can create p- transistors
In a n- substrate, a p- well creates a local p- type substrate region, to
accommodate the n- transistors.
Hence, every p- device is surrounded by an n- well, that must be
connected to VDD via a VDD substrate contact.
Similarly, n- devices are surrounded by p- well connected to GND
using a GND substrate contact.
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132
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PWellsandNWells
IN
P substrate
contact [P+]
n+
OUT
D
n+
P-well
N substrate
contact [n+]
S
p+
G
p+
N-well
A p- transistor is built on an n- substrate and an n- transistor is

built on a p-substrate
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MASKforCMOSInverter
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134
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NWellCMOSInverter
1
SubstrateSelectionSi(100)
10
Lithography(MASK2)
CleaningoftheSubstrate
11
PolySiPatterning
Oxidation(1m)
12
Lithography(MASK3)
Lithography(MASK1)
13
HF(Oxide)Cleaning&PREtching
14
Ionimplantation NMOS
NWellimplantation
15
Repeat12to14forPMOS
OxideEtching
16
DepositionofThickOxide
GateOxideDeposition
17
LithographyandOxidePatterning
PolySiDeposition
18
MetallizationandPatterning
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135
1.SelectionofSubstrate
Si(100)
Ptype
The n-well CMOS process starts with a moderately

doped (with impurity concentration typically less than
1015 cm-3)
P-type silicon substrate.
2.CleaningofSubstrate
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136
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3.Oxidation(1m)
SiO2
Si(100)
P type
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Lithography(MASK1)
UV
MASK1
PositivePhotoresist
SiO2
Si(100)
P type
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138
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HF(Oxide) Cleaning & PR Etching
SiO2
Si(100)
P type
SiO2
Si(100)
P type
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139

SiO2
Si(100)
P type
N-Well Implantation
N-type impurity implantation
SiO2
Si(100)
P type
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NWell
140
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OxideCleaning
Si(100)
P type
NWell
GateOxidation
Si(100)
P type
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NWell
141
PolySiliconDeposition
Si(100)
P type
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NWell
142
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Lithography(MASK2)
Si(100)
P type
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Si(100)
P type
Si(100)
P type
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NWell
143
NWell
NWell
144
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Lithography(MASK3)
Si(100)
P type
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NWell
145
Remove the PR
Si(100)
P type
Si(100)
P type
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NWell
NWell
146
73
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IonImplantation
N+
N+
N+
NWell
Si(100)
P type
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147
Repeat12to14forPMOS
P+
N+
Si(100)
P type
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N+
P+
P+
N+
NWell
148
74
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ThickOxideDeposition
P+
N+
N+
P+
P+
N+
NWell
Si(100)
P type
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149
P+
N+
Si(100)
P type
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N+
P+
P+
N+
NWell
150
75
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VDD
VSS
P+
N+
Si(100)
P type
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N+
P+
P+
N+
NWell
151
TwinTubCMOSFabrication
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152
76
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1.SelectionofSubstrate
Si(100)
Ntype
The twin-tub CMOS process starts with a high resistive

n-type (100) silicon substrate.
2.CleaningofSubstrate
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153
EpitaxialLayerDeposition
Epitaxiallayer
Si(100)
Ntype
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154
77
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3.Oxidation(1m)
SiO2
Epitaxiallayer
Si(100)
Ntype
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155
Lithography(MASK1)
UV
MASK1
PositivePhotoresist
SiO2
Si(100)
Ntype
90
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156
78
9/5/2015
SiO2
Si(100)
Ntype
90
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157
SiO2
Si(100)
Ntype
9/5/2015
158
79
9/5/2015

SiO2
Si(100)
P type
Si(100)
Ntype
90
9/5/2015
N-Well Implantation
159
N-type impurity implantation
SiO2
NWell
Si(100)
Ntype
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160
80
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OxideCleaning
PWell
NWell
Si(100)
Ntype
GateOxidation
PWell
NWell
Si(100)
Ntype
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161
PolySiliconDeposition
PWell
NWell
Si(100)
Ntype
9/5/2015
162
81
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Lithography(MASK2)
PWell
NWell
Si(100)
Ntype
9/5/2015
PWell
163
NWell
Si(100)
Ntype
PWell
NWell
Si(100)
Ntype
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164
82
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Lithography(MASK3)
PWell
NWell
Si(100)
Ntype
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PWell
165
NWell
Si(100)
Ntype
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90
166
83
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IonImplantation
N+
N+
N+
NWell
PWell
Si(100)
Ntype
9/5/2015
P+
PWell
N+
N+
P+
167
P+
N+
NWell
Si(100)
Ntype
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168
84
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ThickOxideDeposition
P+
N+
N+
P+
P+
N+
NWell
PWell
Si(100)
Ntype
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169
P+
PWell
N+
N+
P+
P+
N+
NWell
Si(100)
Ntype
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170
85
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VDD
VSS
+
PP+
PWell
N++
N++
P+
P+
N+
NWell
Si(100)
Ntype
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LatchUp
Tendency of CMOS chips to

develop low-resistance paths
between VDD and VSS Called
Latch-up
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86
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LatchUp
These BJTs form a silicon-controlled
rectifier (SCR) with positive feedback
and virtually short circuit the power rail
to-ground, thus causing excessive
current flows and even permanent
device damage.
PNP transistor whose base is formed
by the n-well with its base-to-collector
current gain (1) as high as several
hundreds.
NPN transistor with its base formed by
the p-type substrate. The base-tocollector current gain 2 of this lateral
transistor may range from a few tenths
to tens
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173
Latchup
Rwell represents the parasitic resistance in the n-well
structure with its value ranging from 1 k to 20 k.
Rsub can be as high as several hundred ohms.
Unless the SCR is triggered by an external disturbance,
the collector currents of both transistors consist of the
reverse leakage currents of the collector-base junctions
and therefore, their current gains are very low.
If the collector current of one of the transistors is
temporarily increased by an external disturbance,
however, the resulting feedback loop causes this current
perturbation to be multiplied by (1 2). This event is called
the
triggering of the SCR.
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87
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Latchup
Once triggered, each transistor drives the other transistor with
positive feedback, eventually creating and sustaining a lowimpedance path between the power and the ground rails,
resulting in latch-up. It can be seen that if the condition
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175
TechniquetoovercomeLatchup
Use p+ guard-band rings connected to ground around
nMOS transistors and n+ guard rings connected to VDD
around pMOS transistors to reduce R and RSUb and to
capture injected minority carriers before they reach the
base of the parasitic BJTs.
Place substrate and well contacts as close as possible to
the source connections of MOS transistors to reduce the
values of Rwell and Rsub.
SOI Devices
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88
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SOIfabrication
Refer: Principles of CMOS VLSI Design A system perspective 2nd Ed. By Neil H. E. We
Kamran Eshraghian Page no. 125-129
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SOIfabrication
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89
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SOIfabrication
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SOIfabrication
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90
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SOIfabrication
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91

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9/5/2015

Basic VLSI Design, 3rd Ed., PHI

CMOS DIGITAL INTEGRATED

CMOS LOGIC CIRCUIT DESIGN

CMOS VLSI Design:A Circuits and Systems

Die area reduces by 50 %

With zero gate bias (VGS=0) , no current flows between source

Small positive voltage applied to gate causes electric field to be

the gate voltage is further increased, at particular voltage VT,

VDS < VGS - Vt

When VDS is applied, the horizontal component of electric field (due

As VDS is increased, the induced Channel acquires a tapered shape and

VDS > VGS - Vt

the gate and the channel region form a parallel plate

consider the infinitesimal strip of the gate at distance x

Charge dq in the infinitesimal portion of the channel at

Negative sign accounts for the fact that dq is a negative

The electric field E(x) causes the electron charge dq to

Where n is the mobility of electrons in the channel (called

Thus i must be equal to the source-to-drain current.

Integrating both sides of this equation from x = 0 to x = L

= electron or hole mobility (surface)

n = 650 cm2/V Sec

The Non-Saturated Region

Determine the Region of Operation of M1

Off because VGS=0V

Non-Saturation VGS Vt =(1-0.4)V=0.6V

Saturation VGS Vt =(1-0.4)V=0.6V

Non-Saturation VGS Vt =(1.5-.4)V=1.1V

Non-Saturation VGS Vt =(1.5-0.4)V=1.1V

Saturation VGS Vt =(0.5-0.4)V=0.1V

Cut-Off VGS =0V

A 0.18-m fabrication process is specified to have

Consider a process technology for which Lmin = 0.4 m,

Kn= 194.1 A/V2

(b) For a MOSFET with W/L= 8 m 0.8 m calculate the

For a 0.8-m process technology for which tox = 15 nm and

A circuit designer intending to operate a MOSFET in

An enhancement type NMOS transistor with Vt = 0.7V

The PMOS transistor shown in Fig. has Vtp=-1V,

>1 is a nonideality factor

PMOS Pass transistor passes strong logic 1.

Maximum output voltage when the output level is logic " 1

This second-order equation in VOL can be solved by temporarily

To satisfy the derivative condition at VIL we differentiate

Determination of pullup to pulldown ratio (Zp.U/

substitute typical values as follows

Vtp = threshold voltage for a pass transistor

Now, for depletion mode p.u. in saturation with VGS = 0

Consider inverter 2 (Figure 2.10(b)) when input = VDD- Vtp.

This image cannot currently be display ed.

This image cannot currently be display ed.

This image cannot currently be display ed.

Taking typical values

Common material used for masks are Photoresist, Polysilicon,

NMOS Fabrication Steps

4.Lithography with MASK1

Photoresist development and Oxide Etching

Poly Silicon Deposition