Design and Implementation of Data Scrambler & Descrambler System Using VHDL
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Editor IJRITCCDesign and Implementation of Data Scrambler & Descrambler System Using VHDL
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Editor IJRITCCInternational Journal on Recent and Innovation Trends in Computing and Communication
Volume: 3 Issue: 6
ISSN: 2321-8169
4162 4167
_______________________________________________________________________________________________
Design and Implementation of Data Scrambler & Descrambler System Using
VHDL
Naina K.Randive
Prof.G.P.Borkhade
Dept.of Electronics and Telecommunications
Dept. of Electronics and Telecommunications
P.R. Pote (Patil) college of Engineering and,
Management Amravati, India
e-mail: naina0689@gmail.com
Dept.of Electronics and Telecommunications
Dept. of Electronics and Telecommunications
P.R. Pote (Patil) college of Engineering and,
Management, Amravati, India
e-mail: gauri.borkhade@gmail.com
Abstract Multimedia data security is very important for multimedia commerce on the internet and real time data multicast. An striking
solution for encrypting data with adequate message security at low cost is the use of Scrambler/Descrambler. Scramblers are necessary
components of physical layer system standards besides interleaved coding and modulation. Scramblers are well used in modern VLSI design
especially those are used in data communication system either to secure data or re-code periodic sequence of binary bits stream. However, it is
necessary to have a descrambler block on the receiving side while using scrambling data in the transmitting end to have the actual input
sequence on the receiving end. Scrambling and De-scrambling is an algorithm that converts an input string into a seemingly random string of the
same length to avoid simultaneous bits in the long format of data. Scramblers have accomplish of uses in today's data communication protocols.
On the other hand, those methods that are theoretical proposed are not feasible in the modern digital design due to many reasons such as slower
data rate, increasing information, circuit hazards, uncountable hold-up etc. Therefore it is requisite for the modern digital design to have
modified architecture to meet the required goal. We will recommend here modified scrambler design which is perfectly suitable for any
industrial design.
Keywords- Scrambler, Descrambler, VHDL, and FPGA.
__________________________________________________*****_________________________________________________
I.
INTRODUCTION
In telecommunications, a scrambler is a device that
transposes or inverts signals or otherwise encodes a message at the
transmitter to make the message unintelligible at a receiver not
equipped with an appropriately set descrambling device. while
encryption usually refers to operations carried out in the digital
domain, scrambling typically refers to operations carried out in the
analog domain. Scrambling is consummate by the addition of
components to the original signal or the changing of some
important component of the original signal in order to make
extraction of the original signal complex .To improve the degree of
data security in a conventional Scrambler the number of stages of the
shift register needs to be enhanced. This conversely increases error
propagation. A uncomplicated method for ensuring security is to
encrypt the data. The pseudo-noise (PN) key generation is of
paramount importance for any secure communication system.
PN sequences base on Linear Feedback Shift Registers (LFSR) and
non linear combination based implementations are simplest to give
moderate level of security. Chaos base encryption techniques have
proved fruitful, but complexity of such systems is important. The
complex system generated is used to scramble incoming plain text. At
the receiving end, the same code be generated and successfully used
to decrypt the transmitted data. The ease of the circuit along with the
complexity of the generated codes makes the circuit striking for
secure message communication applications.
II.
PROPOSED WORK
The entire operation is proposed using Modelsim and Xilinx blocks
goes through three phases.
1.Architecture of Scrambler & Descrambler
2.Block diagram od Scrambler & Descrambler
3.Overview of Scrambler & Descrambler
1.ARCHITECTURE OF SCRAMBLER & DESCRAMBLER
P.T
P.T
Fig1-Architecture of Scrambler and Descrambler
A data scramble & descramble are shown in fig. The
scramble operates in the following manner. The initial shift register
contents are random but prespecified and fixed to the same in both
the scramble and descramble. The initial bit sequence of location 6 &
7 in the shift register X-OR is placed in shift register stage 0.The
generated bit sequence is the sum with plain text, then it becomes the
bit sequence is crypto word. As this bit is presented to the channel the
contents of the shift register are shifted up one stage as follows:
7out,56,45,34,23,12.
The descramble operates as follows. The initial shift
register contents are random but prespecified and fixed to the same
in both the scramble and descramble.The initial bit sequence of
location 6 & 7 in the shift register X-OR is placed in shift register
stage 0.The generated bit sequence is the sum with crypto word then
it becomes the bit sequence is plain text. As this bit is presented to the
channel the contents of the shift register are shifted up one stage as
follows: 7out,56,45,34,23,12.
4162
IJRITCC | June 2015, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
International Journal on Recent and Innovation Trends in Computing and Communication
Volume: 3 Issue: 6
ISSN: 2321-8169
4162 4167
_______________________________________________________________________________________________
2.BLOCK DIAGRAM OF SCRAMBLER & DESCRAMBLER
Fig2:Block diagram of scrambler And descrambler
Block diagram of scramble & descramble represented in
Figure. Scrambler is performed in sequence X-OR the 8-bit plain text
(D0-D7) character with the 8-bit (D0-D7) output of the LFSR. An
output of the LFSR is XOR with plain text of the data to be
processed. The LFSR and data register are then successively
advanced and the output processing is repeated for D1 through D7.
Descrambler is performed in order XOR the 8-bit crypt
word (D0-D7) character with the 8-bit (D0-D7) output of the LFSR.
An output of the LFSR is XOR with crypto word of the data to be
processed. The LFSR and data register are then consecutively
advanced and the output processing is repeated for D1 through D7.
Fig5-RTL Schematic for Scrambler
3. Overview Of Scrambler And Descrambler
In the transmitter, a pseudorandom cipher sequence is
added (modulo 2) to the data (or control) sequence to produce a
scrambled data (or control) sequence.
In the receiver, the same pseudorandom cipher sequence is subtracted
(modulo 2) from the scrambled data (or control) sequence to recover
the transmitted data (or control) sequence, as illustrated in figure.
Pseudorandom
cipher sequence
seseq
P.T
Pseudorandom
+
cipher sequence
Pseudorandom
cipher sequence
C.T
P.T
Fig3-Overview of scrambler and descrambler
uence
III.
RESULTS
Fig6-Internal View of RTL Schematic for Scrambler
The proposed Fpga implementation of various outputs is done using
Modelsim and Xilinx.Both hardware and software implementation of
various output is tabulated below.
A. For 8 bit Scrambler
Fig4-Wave output for Scrambler
Fig7-Internal View of RTL Schematic for Scrambler
4163
IJRITCC | June 2015, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
International Journal on Recent and Innovation Trends in Computing and Communication
Volume: 3 Issue: 6
ISSN: 2321-8169
4162 4167
_______________________________________________________________________________________________
Fig11-Internal View of RTL Schematic for Descrambler
Fig8-View Technology Schematic for Scrambler
Area for Scrmabler
Fig9-Area for Scrambler
Timing summary for Scrambler
Minimum period=3.424ns(Maximum Frequency 292.056MHz)
Throughput for 8 bit scrambler:- Maximum Freq*No of Bit/No of
cycle
=292.056MHz*8/1
Fig12-Internal View of RTL Schematic for Descrambler
=2336.448MHz
~2.4GHz
Fig13-View Technology Schematic for Descrambler
Fig10-RTL Schematic for Descrambler
4164
IJRITCC | June 2015, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
International Journal on Recent and Innovation Trends in Computing and Communication
Volume: 3 Issue: 6
ISSN: 2321-8169
4162 4167
_______________________________________________________________________________________________
C. Maximum Length polynomial for Desrambler
For Enhanced Security using polynomial equation
X7+X6+X4+X3+1=0
Fig14-Internal View Of View technology Schmatic for
Descrambler
Area for Scrmabler
Fig17-Wave output for Maximum Length Polynomial for
Descrambler
D. For 16 Bit Scrambler
Area for 16bit Scrambler
Fig15-Area for Scrambler
Timing summary for Scrambler
Minimum period=3.424ns(Maximum Frequency 292.056MHz)
Throughput for 8 bit scrambler:- Maximum Freq*No of Bit/No of
cycle
=292.056MHz*8/1
Fig18-Area for 16Bit Scrambler
Timing Summary:
Minimum period=3.424ns(Maximum Frequency 292.056MHz)
E. For 32 Bit Scrambler
=2336.448MHz
Area for 32 Bit Scrambler
~2.4GHz
B. Maximum Length polynomial for Scrambler
For Enhanced Security using polynomial equation
X7+X6+X4+X3+1=0
Fig19-Area for 32Bit Scrambler
Fig16-Wave output for Maximum Length polynomial for
Scrambler
Timing Summary:
Minimum period=3.424ns(Maximum Frequency 292.056 MHz)
4165
IJRITCC | June 2015, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
International Journal on Recent and Innovation Trends in Computing and Communication
Volume: 3 Issue: 6
ISSN: 2321-8169
4162 4167
_______________________________________________________________________________________________
F. For 16 Bit Scrambler
Area for 16bit Scrambler
Fig21-Area for 32Bit Scrambler
Timing summary:
Fig20-Area for 16Bit Scrambler
Number Of Bit
Timing Summary:
Minimum period=3.424ns(Maximum Frequency 292.056MHz)
Maxmum Frequency
8 Bit
292.056MHz
16 Bit
292.056MHz
32 Bit
292.056 MHz
8 Bit
449.438MHz
G. For 32 Bit Scrambler
Area for 32 Bit Scrambler
Timing Summary:
Minimum period=3.424ns(Maximum Frequency 292.056 MHz)
H. IMPLEMENTATION
Fig22-Device utilization Summary
Fig23-Timing Summary
4166
IJRITCC | June 2015, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
International Journal on Recent and Innovation Trends in Computing and Communication
Volume: 3 Issue: 6
ISSN: 2321-8169
4162 4167
_______________________________________________________________________________________________
CONCLUSION
A new modified scheme for complex PN-code based data
scrambler and descrambler has been presented. A scrambler &
descrambler accepts information in intelligible form and through
intellectual transformation assure data quality with fastest rate
without any error or dropping occurrence. We used our proposed
and modified design in our present universal serial bus architecture.
Moreover, this current design is very efficient, more securable
,high speed, low power and lower area used & it has lots of scope
to improved.
ACKNOWLEDGMENT
I have taken efforts in this project. Though it would not have been
possible without the kind support and help of many individuals and
organizations. I would like to make bigger my sincere thanks to all
of them. I am highly indebted to Prof .G. P. Borkhade for their
guidance and constant supervision as well as for providing
necessary information regarding the project & also for their support
in completing the project.
I would like to convey my pleasure towards my guide & member
of Electronics and Telecommunication Engineering for their kind
co-operation and encouragement which help me in completion of
this project.
[3] G.M. Bhat, M. Mustafa, Shabir Ahmad, and Javaid
Ahmad,2009, VHDL modeling and simulation of
data scrambler and descrambler for secure data
communication.
[4] Sharma, D.P.Singh J, Simulation and spectral
analysis of the scrambler for 56Kbps modem. The
Journal of Signal Processing Systems. 67, 269-277
(2012).
[5] Sharma, D.P.Singh J.DSP based implementation of
scrambler for 56Kbps modem. Signal Processing
An International Journal. 4, 85-96 (2010).
[6] Hethan Kumar, M Praveen Kumar Y G, Dr. M
volume 3 Issue 4,April 2014, Design and
implementation of Logical Scrambler Architecture
for OTN Protocol.
[7] Xiao-Bei Liu, Soo Ngee Koh, Chee-Cheon Chui,
and Xin-Wen Wu, A Study of Reconstruction of
Linear Scrambler using Dual Words of Channel
Encoder March 2013.
I would like to express my special gratitude and thanks to institute
persons for giving me such attention and time.My thanks and
appreciations also go to my colleague in developing the project and
people who have willingly helped me out with their abilities.
REFERANCES
[1] Rajib Imranand Monirul Islam,2013,Indurtial
Modified Digital scrambler and descrambler
system.
[2] Davinder Pal Sharma,2013, Data scrambler of
ultra-wide band communication system.
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