Chapter 3
Chapter 3
Microelectronics
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Chapter 3-1
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Chapter 3-2
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Chapter 3-3
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Chapter 3-4
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Schematic of n-Channel
Enhancement Mode MOSFET
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Chapter 3-5
After electron
inversion layer is
formed
Before electron
inversion layer is
formed
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Chapter 3-6
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Chapter 3-7
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Chapter 3-8
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Chapter 3-9
p-Channel Enhancement-Mode
MOSFET
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Chapter 3-10
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Chapter 3-11
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Chapter 3-12
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Chapter 3-13
Symbols
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Chapter 3-14
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Symbols
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Chapter 3-15
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Chapter 3-16
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NMOS
PMOS
Nonsaturation vDS<vDS(sat)
vSD<vSD(sat)
2
2
]
iD K n [2(vGS VTN )vDS vDS
] iD K p [2(vSG VTP )vSD vSD
Saturation
vDS>vDS(sat)
vSD>vSD(sat)
iD K n [vGS VTN ]2
iD K p [vSG VTP ]2
Transition Pt.
Enhancement
Mode
VTN > 0V
VTP < 0V
Depletion
Mode
VTN < 0V
VTP > 0V
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Chapter 3-17
Conduction Parameters
NMOSFET
Kn
PMOSFET
Kp
where:
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W nCox
W
k n'
L
L
W p Cox
L
k p'
W
L
Cox o tox
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Chapter 3-18
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Chapter 3-19
Body Effect
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Chapter 3-20
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Subthreshold Condition
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Chapter 3-21
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Chapter 3-22
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Chapter 3-23
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Chapter 3-24
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Problem-Solving Technique:
NMOSFET DC Analysis
1. Assume the transistor is in saturation.
a. VGS > VTN, ID > 0, & VDS VDS(sat)
2. Analyze circuit using saturation I-V relations.
3. Evaluate resulting bias condition of transistor.
a. If VGS < VTN, transistor is likely in cutoff
b. If VDS < VDS(sat), transistor is likely in
nonsaturation region
4. If initial assumption is proven incorrect, make
new assumption and repeat Steps 2 and 3.
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Chapter 3-25
Kn = 1mA/V2
VTN = 1V
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Chapter 3-26
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ML is always in
saturation.
MD can be biased
either in saturation or
nonsaturation region.
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Chapter 3-27
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vI > VTN
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Chapter 3-28
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Chapter 3-29
CMOS Inverter
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Chapter 3-30
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V1 (V)
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V2 (V) VO (V)
High
Low
Low
Low
Chapter 3-31
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Chapter 3-32
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Current
Mirrors
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Chapter 3-33
Common-source
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Chapter 3-34
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Chapter 3-35
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Chapter 3-36
18
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Chapter 3-37
19