ICL8038

Data Sheet September 1998 File Number 2864.3

Precision Waveform Generator/Voltage Features

Controlled Oscillator Low Frequency Drift with Temperature . . . . . . .250ppm/oC
The ICL8038 waveform generator is a monolithic integrated Low Distortion. . . . . . . . . . . . . . . . 1% (Sine Wave Output)
circuit capable of producing high accuracy sine, square,
High Linearity . . . . . . . . . . . 0.1% (Triangle Wave Output)
triangular, sawtooth and pulse waveforms with a minimum of
external components. The frequency (or repetition rate) can Wide Frequency Range . . . . . . . . . . . 0.001Hz to 300kHz
be selected externally from 0.001Hz to more than 300kHz Variable Duty Cycle . . . . . . . . . . . . . . . . . . . . . 2% to 98%
using either resistors or capacitors, and frequency
modulation and sweeping can be accomplished with an High Level Outputs . . . . . . . . . . . . . . . . . . . . . . TTL to 28V
external voltage. The ICL8038 is fabricated with advanced Simultaneous Sine, Square, and Triangle Wave
monolithic technology, using Schottky barrier diodes and thin Outputs
film resistors, and the output is stable over a wide range of
Easy to Use - Just a Handful of External Components
temperature and supply variations. These devices may be
Required
interfaced with phase locked loop circuitry to reduce
temperature drift to less than 250ppm/oC.

Ordering Information
PART NUMBER STABILITY TEMP. RANGE (oC) PACKAGE PKG. NO.

ICL8038CCPD 250ppm/oC (Typ) 0 to 70 14 Ld PDIP E14.3

ICL8038CCJD 250ppm/oC (Typ) 0 to 70 14 Ld CERDIP F14.3

ICL8038BCJD 180ppm/oC (Typ) 0 to 70 14 Ld CERDIP F14.3

ICL8038ACJD 120ppm/oC (Typ) 0 to 70 14 Ld CERDIP F14.3

Pinout Functional Diagram

ICL8038
V+
(PDIP, CERDIP) 6
TOP VIEW CURRENT
SOURCE
#1 COMPARATOR
I #1
SINE WAVE 1 14 NC 10
ADJUST
SINE 2I
2 13 NC C COMPARATOR
WAVE OUT
#2
TRIANGLE
3 12 SINE WAVE
OUT ADJUST

DUTY CYCLE 4 11 V- OR GND

FREQUENCY
ADJUST 5 10 TIMING CURRENT
CAPACITOR SOURCE FLIP-FLOP
6 9 SQUARE #2
V+
WAVE OUT V- OR GND
FM SWEEP 11
FM BIAS 7 8
INPUT
SINE
BUFFER BUFFER CONVERTER

9 3 2

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
 ICL8038

Absolute Maximum Ratings Thermal Information

Supply Voltage (V- to V+). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W)
Input Voltage (Any Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+ CERDIP Package. . . . . . . . . . . . . . . . . 75 20
Input Current (Pins 4 and 5). . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA PDIP Package . . . . . . . . . . . . . . . . . . . 115 N/A
Output Sink Current (Pins 3 and 9) . . . . . . . . . . . . . . . . . . . . . 25mA Maximum Junction Temperature (Ceramic Package) . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Operating Conditions Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Temperature Range
ICL8038AC, ICL8038BC, ICL8038CC . . . . . . . . . . . . 0oC to 70oC
Die Characteristics
Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications VSUPPLY = 10V or +20V, TA = 25oC, RL = 10k, Test Circuit Unless Otherwise Specified

ICL8038CC ICL8038BC ICL8038AC

TEST
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

Supply Voltage Operating Range VSUPPLY

V+ Single Supply +10 - +30 +10 - +30 +10 - +30 V

V+, V- Dual Supplies 5 - 15 5 - 15 5 - 15 V

Supply Current ISUPPLY VSUPPLY = 10V 12 20 - 12 20 - 12 20 mA

(Note 2)

FREQUENCY CHARACTERISTICS (All Waveforms)

Max. Frequency of Oscillation fMAX 100 - - 100 - - 100 - - kHz

Sweep Frequency of FM Input fSWEEP - 10 - - 10 - - 10 - kHz

Sweep FM Range (Note 3) - 35:1 - - 35:1 - - 35:1 -

FM Linearity 10:1 Ratio - 0.5 - - 0.2 - - 0.2 - %

Frequency Drift with f/T 0oC to 70oC - 250 - - 180 - - 120 ppm/oC
Temperature (Note 5)
Frequency Drift with Supply Voltage f/V Over Supply - 0.05 - - 0.05 - 0.05 - %/V
Voltage Range

OUTPUT CHARACTERISTICS

Square Wave
Leakage Current IOLK V9 = 30V - - 1 - - 1 - - 1 A

Saturation Voltage VSAT ISINK = 2mA - 0.2 0.5 - 0.2 0.4 - 0.2 0.4 V

Rise Time tR RL = 4.7k - 180 - - 180 - - 180 - ns

Fall Time tF RL = 4.7k - 40 - - 40 - - 40 - ns

Typical Duty Cycle Adjust D 2 98 2 - 98 2 - 98 %

(Note 6)

Triangle/Sawtooth/Ramp -
Amplitude VTRIAN- RTRI = 100k 0.30 0.33 - 0.30 0.33 - 0.30 0.33 - xVSUPPLY
GLE

Linearity - 0.1 - - 0.05 - - 0.05 - %

Output Impedance ZOUT IOUT = 5mA - 200 - - 200 - - 200 -

2
 ICL8038

Electrical Specifications VSUPPLY = 10V or +20V, TA = 25oC, RL = 10k, Test Circuit Unless Otherwise Specified (Continued)

ICL8038CC ICL8038BC ICL8038AC

TEST
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

Sine Wave
Amplitude VSINE RSINE = 100k 0.2 0.22 - 0.2 0.22 - 0.2 0.22 - xVSUPPLY

THD THD RS = 1M - 2.0 5 - 1.5 3 - 1.0 1.5 %

(Note 4)

THD Adjusted THD Use Figure 4 - 1.5 - - 1.0 - - 0.8 - %

NOTES:
2. RA and RB currents not included.
3. VSUPPLY = 20V; RA and RB = 10k, f 10kHz nominal; can be extended 1000 to 1. See Figures 5A and 5B.
4. 82k connected between pins 11 and 12, Triangle Duty Cycle set at 50%. (Use RA and RB.)
5. Figure 1, pins 7 and 8 connected, VSUPPLY = 10V. See Typical Curves for T.C. vs VSUPPLY.
6. Not tested, typical value for design purposes only.

Test Conditions
PARAMETER RA RB RL C SW1 MEASURE

Supply Current 10k 10k 10k 3.3nF Closed Current Into Pin 6

Sweep FM Range (Note 7) 10k 10k 10k 3.3nF Open Frequency at Pin 9

Frequency Drift with Temperature 10k 10k 10k 3.3nF Closed Frequency at Pin 3

Frequency Drift with Supply Voltage (Note 8) 10k 10k 10k 3.3nF Closed Frequency at Pin 9

Output Amplitude (Note 10)

Sine 10k 10k 10k 3.3nF Closed Pk-Pk Output at Pin 2

Triangle 10k 10k 10k 3.3nF Closed Pk-Pk Output at Pin 3

Leakage Current (Off) (Note 9) 10k 10k 3.3nF Closed Current into Pin 9

Saturation Voltage (On) (Note 9) 10k 10k 3.3nF Closed Output (Low) at Pin 9

Rise and Fall Times (Note 11) 10k 10k 4.7k 3.3nF Closed Waveform at Pin 9

Duty Cycle Adjust (Note 11)

Max 50k ~1.6k 10k 3.3nF Closed Waveform at Pin 9

Min ~25k 50k 10k 3.3nF Closed Waveform at Pin 9

Triangle Waveform Linearity 10k 10k 10k 3.3nF Closed Waveform at Pin 3

Total Harmonic Distortion 10k 10k 10k 3.3nF Closed Waveform at Pin 2

NOTES:
7. The hi and lo frequencies can be obtained by connecting pin 8 to pin 7 (fHI) and then connecting pin 8 to pin 6 (fLO). Otherwise apply Sweep
Voltage at pin 8 (2/3 VSUPPLY +2V) VSWEEP VSUPPLY where VSUPPLY is the total supply voltage. In Figure 5B, pin 8 should vary between
5.3V and 10V with respect to ground.
8. 10V V+ 30V, or 5V VSUPPLY 15V.
9. Oscillation can be halted by forcing pin 10 to +5V or -5V.
10. Output Amplitude is tested under static conditions by forcing pin 10 to 5V then to -5V.
11. Not tested; for design purposes only.

3
 ICL8038

Test Circuit
+10V
RA RB RL
10K 10K 10K

7 4 5 6 9
SW1
N.C.

8 ICL8038 3
RTRI

10 11 12 2

C RSINE
82K
3300pF
-10V
FIGURE 1. TEST CIRCUIT

Detailed Schematic
CURRENT SOURCES 6
V+
R41 R32
REXT B REXT A
R1 4K 5.2K
8 Q1 5
11K 4 Q14
Q2 Q48 1
7 R8
Q3 Q47 R33
R2 5K
Q R19 200
39K 6 Q4 Q5 Q46

COMPARATOR 800 Q45 R34

Q7 R20 375
Q8 Q9 Q44
10
Q15 Q18 2.7K
R46 Q43 R35
R21
40K
CEXT Q16Q17 330
R9 Q42
5K 10K
R7B R7A Q41
Q10
R3 R25 R26 R27 R45
Q11 15K 10K
30K 33K 33K 33K 33K
Q12 R36
Q30
Q13 Q20 Q21 1600
Q31 Q19 Q22
R4 R5 R6 R28 R29 R30 R31
Q32 100 100 100 R10 33K 33K 33K 33K
5K Q49
Q33 R22
Q50
Q34
R13 R16 R43 10K Q51 R37
620 1.8K 27K R23 330
Q24 Q52
9 R14 Q37 2.7K Q53 R38
Q35 Q39
27K R24 375
R11 Q36 Q Q54
270 38 Q40
R41 3 R44 800 R39
Q26 Q Q55
Q23 Q27 28 200
27K 1K 12
R12 R15 R17 Q56
2.7K 470 4.7K R40
R42 REXTC
Q25 Q29 BUFFER AMPLIFIER 2 5.6K
27K 11 82K
R18
4.7K SINE CONVERTER
FLIP-FLOP

Application Information (See Functional Diagram) net-current I and the voltage across it drops linearly with time.
When it has reached the level of comparator #2 (set at 1/3 of
An external capacitor C is charged and discharged by two
the supply voltage), the flip-flop is triggered into its original
current sources. Current source #2 is switched on and off by a
state and the cycle starts again.
flip-flop, while current source #1 is on continuously. Assuming
that the flip-flop is in a state such that current source #2 is off, Four waveforms are readily obtainable from this basic
and the capacitor is charged with a current I, the voltage generator circuit. With the current sources set at I and 2I
across the capacitor rises linearly with time. When this voltage respectively, the charge and discharge times are equal. Thus
reaches the level of comparator #1 (set at 2/3 of the supply a triangle waveform is created across the capacitor and the
voltage), the flip-flop is triggered, changes states, and flip-flop produces a square wave. Both waveforms are fed to
releases current source #2. This current source normally buffer stages and are available at pins 3 and 9.
carries a current 2I, thus the capacitor is discharged with a

4
 ICL8038

The levels of the current sources can, however, be selected

CV C 1/3 V SUPPLY R A RA C
over a wide range with two external resistors. Therefore, with t 1 = -------------- = ------------------------------------------------------------------- = ------------------
I 0.22 V SUPPLY 0.66
the two currents set at values different from I and 2I, an
The falling portion of the triangle and sine wave and the 0
asymmetrical sawtooth appears at Terminal 3 and pulses
state of the square wave is:
with a duty cycle from less than 1% to greater than 99% are
CV C 1/3V SUPPLY R R C
A B
available at Terminal 9. t = ------------- = ----------------------------------------------------------------------------------- = --------------------------------------
2 1 V
SUPPLY
V
SUPPLY 0.66 ( 2R A R B )
2 ( 0.22 ) ------------------------ 0.22 ------------------------
The sine wave is created by feeding the triangle wave into a R
B
R
A
nonlinear network (sine converter). This network provides a Thus a 50% duty cycle is achieved when RA = RB.
decreasing shunt impedance as the potential of the triangle
If the duty cycle is to be varied over a small range about 50%
moves toward the two extremes.
only, the connection shown in Figure 3B is slightly more
Waveform Timing convenient. A 1k potentiometer may not allow the duty cycle
The symmetry of all waveforms can be adjusted with the to be adjusted through 50% on all devices. If a 50% duty cycle
external timing resistors. Two possible ways to accomplish is required, a 2k or 5k potentiometer should be used.
this are shown in Figure 3. Best results are obtained by With two separate timing resistors, the frequency is given by:
keeping the timing resistors RA and RB separate (A). RA 1 1
f = ---------------- = ------------------------------------------------------
controls the rising portion of the triangle and sine wave and t1 + t2 RA C RB
------------ 1 + -------------------------
the 1 state of the square wave. 0.66 2R A R B

The magnitude of the triangle waveform is set at 1/3 or, if RA = RB = R

VSUPPLY; therefore the rising portion of the triangle is, 0.33
f = ----------- (for Figure 3A)
RC

FIGURE 2A. SQUARE WAVE DUTY CYCLE - 50% FIGURE 2B. SQUARE WAVE DUTY CYCLE - 80%
FIGURE 2. PHASE RELATIONSHIP OF WAVEFORMS

V+
V+
1k RL
RA RB RL RA RB

7 4 5 6 9 4 5 6
7 9

8 ICL8038 3 8 ICL8038 3

10 11 12 2 10 11 12 2

C 82K C 100K
V- OR GND V- OR GND
FIGURE 3A. FIGURE 3B.
FIGURE 3. POSSIBLE CONNECTIONS FOR THE EXTERNAL TIMING RESISTORS

5
 ICL8038

Neither time nor frequency are dependent on supply voltage, R1 and R2 are shown in the Detailed Schematic.
even though none of the voltages are regulated inside the
A similar calculation holds for RB.
integrated circuit. This is due to the fact that both currents
and thresholds are direct, linear functions of the supply The capacitor value should be chosen at the upper end of its
voltage and thus their effects cancel. possible range.

Reducing Distortion Waveform Out Level Control and Power Supplies

To minimize sine wave distortion the 82k resistor between The waveform generator can be operated either from a
pins 11 and 12 is best made variable. With this arrangement single power supply (10V to 30V) or a dual power supply
distortion of less than 1% is achievable. To reduce this even (5V to 15V). With a single power supply the average levels
further, two potentiometers can be connected as shown in of the triangle and sine wave are at exactly one-half of the
Figure 4; this configuration allows a typical reduction of sine supply voltage, while the square wave alternates between
wave distortion close to 0.5%. V+ and ground. A split power supply has the advantage that
all waveforms move symmetrically about ground.

V+ The square wave output is not committed. A load resistor

RA
1k
RB RL can be connected to a different power supply, as long as the
applied voltage remains within the breakdown capability of
7 4 5 6 9 the waveform generator (30V). In this way, the square wave
output can be made TTL compatible (load resistor
connected to +5V) while the waveform generator itself is
8 ICL8038 3
powered from a much higher voltage.

Frequency Modulation and Sweeping

10 11 12 1 2
The frequency of the waveform generator is a direct function
100k 10k
of the DC voltage at Terminal 8 (measured from V+). By
C
100k altering this voltage, frequency modulation is performed. For
10k small deviations (e.g. 10%) the modulating signal can be
applied directly to pin 8, merely providing DC decoupling
V- OR GND with a capacitor as shown in Figure 5A. An external resistor
FIGURE 4. CONNECTION TO ACHIEVE MINIMUM SINE WAVE between pins 7 and 8 is not necessary, but it can be used to
DISTORTION increase input impedance from about 8k (pins 7 and 8
connected together), to about (R + 8k).
Selecting RA, RB and C
For larger FM deviations or for frequency sweeping, the
For any given output frequency, there is a wide range of RC
modulating signal is applied between the positive supply
combinations that will work, however certain constraints are
voltage and pin 8 (Figure 5B). In this way the entire bias for
placed upon the magnitude of the charging current for
the current sources is created by the modulating signal, and
optimum performance. At the low end, currents of less than
a very large (e.g. 1000:1) sweep range is created (f = 0 at
1A are undesirable because circuit leakages will contribute
VSWEEP = 0). Care must be taken, however, to regulate the
significant errors at high temperatures. At higher currents
supply voltage; in this configuration the charge current is no
(I > 5mA), transistor betas and saturation voltages will
longer a function of the supply voltage (yet the trigger
contribute increasingly larger errors. Optimum performance
thresholds still are) and thus the frequency becomes
will, therefore, be obtained with charging currents of 10A to
dependent on the supply voltage. The potential on Pin 8 may
1mA. If pins 7 and 8 are shorted together, the magnitude of
be swept down from V+ by (1/3 VSUPPLY - 2V).
the charging current due to RA can be calculated from:
R 1 ( V+ V- ) 1 0.22 ( V+ V- )
I = ---------------------------------------- -------- = ------------------------------------
( R1 + R2 ) RA RA

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

6
 ICL8038

V+ With a dual supply voltage the external capacitor on Pin 10 can

RL
be shorted to ground to halt the ICL8038 oscillation. Figure 7
RA RB
shows a FET switch, diode ANDed with an input strobe signal
to allow the output to always start on the same slope.
7 4 5 6 9

R V+

8 ICL8038 3 RA RB 15K

7 4 5 9
FM
10 11 12 2

C 81K 8 ICL8038
1N914
V- OR GND

2
FIGURE 5A. CONNECTIONS FOR FREQUENCY MODULATION 11 10

1N914
C 2N4392 STROBE
V+
100K
-15V
SWEEP RA RB RL OFF
VOLTAGE +15V (+10V)
-15V (-10V)
4 5 6 9 ON

FIGURE 7. STROBE TONE BURST GENERATOR

8 ICL8038 3
To obtain a 1000:1 Sweep Range on the ICL8038 the
voltage across external resistors RA and RB must decrease
to nearly zero. This requires that the highest voltage on
10 11 12 2
control Pin 8 exceed the voltage at the top of RA and RB by a
C 81K few hundred mV. The Circuit of Figure 8 achieves this by
using a diode to lower the effective supply voltage on the
V- OR GND
ICL8038. The large resistor on pin 5 helps reduce duty cycle
FIGURE 5B. CONNECTIONS FOR FREQUENCY SWEEP variations with sweep.
FIGURE 5.
The linearity of input sweep voltage versus output frequency
can be significantly improved by using an op amp as shown
Typical Applications in Figure 10.
The sine wave output has a relatively high output impedance
(1k Typ). The circuit of Figure 6 provides buffering, gain +10V

and amplitude adjustment. A simple op amp follower could 1N457

also be used. DUTY CYCLE

0.1F 15K
1K
V+ 4.7K 4.7K

RA RB

AMPLITUDE 5 4 6 9
7 4 5 6 2

+
100K 741 10K
FREQ. 8 ICL8038 3
8 ICL8038 -
20K

4.7K 10 11 12 2
10 11

C
20K 15M 0.0047F DISTORTION
100K
-10V
V-

FIGURE 8. VARIABLE AUDIO OSCILLATOR, 20Hz TO 20kHzY

FIGURE 6. SINE WAVE OUTPUT BUFFER AMPLIFIERS

7
 ICL8038

V2+
DUTY
CYCLE
R1
FREQUENCY TRIANGLE
ADJUST OUT
FM BIAS
V1+ 6
7 4 5 3
SQUARE SINE WAVE
WAVE OUT
OUT
9 ICL8038 2

VCO DEMODULATED
IN SINE WAVE
INPUT PHASE AMPLIFIER FM 1
8 10 11 12 ADJ.
DETECTOR R2

TIMING SINE WAVE

CAP. ADJ.
LOW PASS
FILTER
V-/GND

FIGURE 9. WAVEFORM GENERATOR USED AS STABLE VCO IN A PHASE-LOCKED LOOP

HIGH FREQUENCY
SYMMETRY
10k 100k
500
1N753A
4.7k 4.7k
(6.2V) 1M
1k 100k
1,000pF LOW FREQUENCY
4 5 6 9 SYMMETRY
+15V

- 1k SINE WAVE
ICL8038 +15V OUTPUT
741 8 3
FUNCTION GENERATOR
+ -
-VIN P4 741
+ +
10 11 12 2
10k 50F
OFFSET 100k 15V
3,900pF SINE WAVE
DISTORTION

-15V

FIGURE 10. LINEAR VOLTAGE CONTROLLED OSCILLATOR

Use in Phase Locked Loops

Its high frequency stability makes the ICL8038 an ideal Second, the DC output level of the amplifier must be made
building block for a phase locked loop as shown in Figure 9. compatible to the DC level required at the FM input of the
In this application the remaining functional blocks, the phase waveform generator (pin 8, 0.8V+). The simplest solution here
detector and the amplifier, can be formed by a number of is to provide a voltage divider to V+ (R1, R2 as shown) if the
available ICs (e.g., MC4344, NE562). amplifier has a lower output level, or to ground if its level is
higher. The divider can be made part of the low-pass filter.
In order to match these building blocks to each other, two
steps must be taken. First, two different supply voltages are This application not only provides for a free-running
used and the square wave output is returned to the supply of frequency with very low temperature drift, but is also has the
the phase detector. This assures that the VCO input voltage unique feature of producing a large reconstituted sinewave
will not exceed the capabilities of the phase detector. If a signal with a frequency identical to that at the input.
smaller VCO signal is required, a simple resistive voltage
For further information, see Intersil Application Note AN013,
divider is connected between pin 9 of the waveform
Everything You Always Wanted to Know About the ICL8038.
generator and the VCO input of the phase detector.

8
 ICL8038

Definition of Terms FM Linearity. The percentage deviation from the best fit
straight line on the control voltage versus output frequency
Supply Voltage (VSUPPLY). The total supply voltage from
curve.
V+ to V-.
Output Amplitude. The peak-to-peak signal amplitude
Supply Current. The supply current required from the
appearing at the outputs.
power supply to operate the device, excluding load currents
and the currents through RA and RB. Saturation Voltage. The output voltage at the collector of
Q23 when this transistor is turned on. It is measured for a
Frequency Range. The frequency range at the square wave
sink current of 2mA.
output through which circuit operation is guaranteed.
Rise and Fall Times. The time required for the square wave
Sweep FM Range. The ratio of maximum frequency to
output to change from 10% to 90%, or 90% to 10%, of its
minimum frequency which can be obtained by applying a
final value.
sweep voltage to pin 8. For correct operation, the sweep
voltage should be within the range: Triangle Waveform Linearity. The percentage deviation
from the best fit straight line on the rising and falling triangle
(2/3 VSUPPLY + 2V) < VSWEEP < VSUPPLY
waveform.

Total Harmonic Distortion. The total harmonic distortion at

the sine wave output.

Typical Performance Curves

20 1.03

1.02
NORMALIZED FREQUENCY
SUPPLY CURRENT (mA)

-55oC
15 1.01

125oC 1.00

10 25oC 0.99

0.98

5
5 10 15 20 25 30 5 10 15 20 25 30
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

FIGURE 11. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 12. FREQUENCY vs SUPPLY VOLTAGE

1.03 200

1.02
NORMALIZED FREQUENCY

RISE TIME
10 150 125oC
1.01 25oC
20
TIME (ns)

30 -55oC
1.00
20
100 125oC
10 30 25oC
0.99 FALL TIME
-55oC
50
0.98

0
-50 -25 0 25 75 125 0 2 4 6 8 10
TEMPERATURE (oC) LOAD RESISTANCE (k)

FIGURE 13. FREQUENCY vs TEMPERATURE FIGURE 14. SQUARE WAVE OUTPUT RISE/FALL TIME vs
LOAD RESISTANCE

9
 ICL8038

Typical Performance Curves (Continued)

2 1.0

NORMALIZED PEAK OUTPUT VOLTAGE

LOAD CURRENT 125oC
TO V -
25oC
SATURATION VOLTAGE

1.5
0.9
-55oC
125oC
1.0
25oC
-55oC
0.8
LOAD CURRENT TO V+
0.5

0
0 2 4 6 8 10 0 2 4 6 8 10 12 14 16 18 20
LOAD CURRENT (mA) LOAD CURRENT (mA)

FIGURE 15. SQUARE WAVE SATURATION VOLTAGE vs LOAD FIGURE 16. TRIANGLE WAVE OUTPUT VOLTAGE vs LOAD
CURRENT CURRENT

1.2 10.0
NORMALIZED OUTPUT VOLTAGE

1.1

1.0 1.0
LINEARITY (%)

0.9

0.8 0.1

0.7

0.6 0.01
10 100 1K 10K 100K 1M 10 100 1K 10K 100K 1M

FREQUENCY (Hz) FREQUENCY (Hz)

FIGURE 17. TRIANGLE WAVE OUTPUT VOLTAGE vs FIGURE 18. TRIANGLE WAVE LINEARITY vs FREQUENCY
FREQUENCY

1.1 12
NORMALIZED OUTPUT VOLTAGE

10
DISTORTION (%)

1.0 8

0.9 4
UNADJUSTED ADJUSTED

0
10 100 1K 10K 100K 1M 10 100 1K 10K 100K 1M
FREQUENCY (Hz) FREQUENCY (Hz)

FIGURE 19. SINE WAVE OUTPUT VOLTAGE vs FREQUENCY FIGURE 20. SINE WAVE DISTORTION vs FREQUENCY

10