iSPLICE3: A New Simulator for Mixed AnalogIDigital Circuits

E. L. Acuna, J. P. Dervenis, A. J . Pagones, R. A. Saleh

C o or din ated Science Lab oratory
University of Illinois.

ABSTRACT 2.2. Electrical-Logic (ELogic) Analysis

This paper describes a new simulator called S P L I C E 3 for the ELogic [KIM841 is an accurate switch-level timing simu-
analysis o f mixed analog/digital circuits. It combines electrical, lation technique. It allows detailed timing informatiou to he
switch-level timing and logic simulation modes using event-driven
selective-trace techniques. It features a hierarchical schematic obtained, sincc it uses electrical device models in tlie context
capture package called iSPI for design entry and simulation con- of switch-level simulation. A s part of the ELogic modeling
trol. It also uses a novel approach t o improve the speed and process, a number of discrete voltage levels are selected.
robustness of the DC solution. The details o f the simulator
architecture, circuit partitioning, mixed-mode interface and event These levels need not be equally spaced but the number of
scheduling are provided in this paper along with the results of levels and their values have an impact on performance and
mixed-mode simulations o f a recent memory circuit. accuracy. The basic idea in ELogic is to compute the rime
required to make a transition from one voltage state to
another adjacent voltage state. Different ELogic models can
1. INTRODUCTION be used in different portions of the circuit to tradeoff accu-
Mixed-mode simulation [NEW81, SAK81, CHE83, racy and speed. Therefore, ELogic by itself provides a
KLE84, GR0871 is becoming a very popular form of simula- mixed-mode simulation capability. However, it should be
tion in industry for large circuits containing both analog and used mainly for switch-level logic circuits where the effect of
digital components, and for circuits described at multiple floating capacitors are not important to the behavior of the
levels of abstraction. The goal of a mixed-mode simulator is circuit.
to allow the designer to intelligently tradeoff simulation accii-
racy for speed within the scope of a single simnlator. A 2.3. 1,ogir Analysis
mixed-mode simulator allows the designer to represent dif- This is the highest level of simulation in the crtrrcnt vcr-
ferent parts of the same circuit at different levels of ahstrac- sion of tlie program. Simple gates such a NANDs, NORs,
tion. The simulator theu combines the different representa- inverters, XOlis, ctc., are available. The rise and fall dclays
tions, models and signal types in one simnlation and pro- can be specified and a fanout dependent delay can also be
duces the desired results while reducing the overall run-time invoked. Adding new logic models to the program is rela-
significantly. tively straight-forward process.
This paper describes iSPLICE3, a new mixed-mode
simulator of MOS and bipolar integrated circuits [DER@], 3. ISPI: A HIERARCHICAL SPLICE INTERFACE
and its schematic capture package iSPI (Splice Interface)
The schematic capture and simulation interface package
[PAG88]. In the sections to follow, the simulation algo-
for iSPLICE3, called iSPI, has been developed within the
rithms and architecture of iSPLICE3 and features of the
Berkeley Design Environment [HAR86] which provides a
schematic interface are described. This is followed a discus-
database manager (Oct), a graphics editor (VEM) and an
sion of a number of mixed-mode interface issues and a
application interface tool (RPC) and allows new CAD tools
description of the D C solution method. In the final sec-
to be easily integrated into the system. iSPI is executed
tions, results and conclusions are provided.
under VEM and allows the designer to enter a hierarchical
description of the circuit to be simulated. That is, transis-
2. OVERVIEW OF TRANSIENT ANALYSIS AI,GOHITHMS tors can be entered and then gronped to form gates which, in
2.1. Iterated Timing Analysis (ITA) torn, can be grouped to form logic blocks, etc. 'The designer
iSI'LICE3 uses iterated timing analysis (ITA) spccifics the simulation mode by choosing different simula-
[S241,83,KLE84] for electrical simulation. I T A is a nom tion layers i n the schematic editor and placing tlie appropri-
1in ear r claxa t ion-based simulat io t i tech t i ique [ S A 1,871 that ate circuitry on the desired layer. In the current implemcn-
exploits circuit latency. It employs variable time-step coiitrol tation of iS1'1, tlierc is an I T A layer, an ELogic layer and a
but uses the same time-step for all active nodes. The active Logic layer. Each layer is associated with a distinct color to
nodes are identified using the selective-trace algorithm. The permit visual consistcncy checking by tlic dcsigncr. In prin-
overall simulation time in iSPLICE3 is usaally a strong futic- ciple, tlie entire design could be rcpresented on every simula-
tion of the number of I T A nodes in the circuit and therefore tion layer, although this rule is not strictly enforced.
it is important to use this type of simulation oiily where it is Once the hierarchical design description has been
critical, such as in memory cells, sense amplifiers, opamps, entered, the simulation level to be used by S P L I C E 3 is
and other analog circuit functions. specified in iSPI wing the "expand-down" or "expand-up"

13.1. I

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commands. T o move circuitry to a higher level of simula- 4.2. Main Simulation Loop
tion, a bounding box is placed around the circuitry and the The main loop of the simulator is embodied in the
"expand-up" command is invoked. All the circuit blocks in "while" loop where the scheduler sequences through a list of
the selected region are moved u p one level in the hierarchy. scheduled events. Each event has an associated time, func-
A similar effect is obtained with the "expand-down'' com- tion and data. When an event is processed, the function is
mand except that the selected objects are moved to a more performed on the data at the prescribed time. New events
detailed level of abstraction. This process is shown in Fig. 1. are scheduled in the queue as part of the call to the simula-
The screen is updated with the appropriate circuitry in tion function. Special simulation related tasks may also be
response to the expand command. When the designer has scheduled in the time queue along with regular simulation
selected the combination of simulation modes for the entire events. This organization makes the addition of new simula-
circuit, the "SPLICE" command is issued and the informa- tion algorithms and functions relatively simple, since the
tion on the screen is passed via the Remote-Procedure-Call structure of the events allows any type of function to be exe-
(RPC) interface to the iSPLICE3 program. Finally, the cuted. Examples of typical functions scheduled in iSPLICE3
results are returned when the simulation is completed. are ita-step(), logicstep(), elogic-step(), get-tinze-step 0,
backup-tinze(), ~tdieup-call()and process-pwl().
4. SPLICE3 ARCHITECTURE
4.3. Circuit Partitioning
4.1. Organization of iSPLICE3 T h e circuit is partitioned into subcircuits in
T h e common framework for the forms of analyses in partition-circuit(). A t the present time, the subcircuit types
S P L I C E 3 is based on event-driven, selective-trace tech- (either LOGIC, E L O G I C , or ITA) are determined by the
niques to exploit latency or temporal sparsity [NEW81, input circuit description provided by the designer.
SAK801. The basic simulation flow of iSPLICE3 is as fol- iSPLICE3 determines the subcircuit type based on the dev-
lows: ices connected to nodes in the circuit. For example, if a
splice3( ) node has only ELogic devices connected to it, then it will be
{ labeled as an ELogic node. If it has only logic devices con-
readin( ); nected to it, then it will be labeled as an Logic node. How-
partition-circuit(); ever, if there is at least one Elogic device controlling the
dc-analysis(); node (i.e., the drain or source of a transistor), it will be
forall ( subcircuits Si in the circuit) labeled as an ELogic node. In this case, all the other non-
schedule ( S i , t=O ); Elogic devices connected to the node will be automatically
I* M A I N S C H E D U L E R LOOP: *I expanded down to the appropriate level to maintain simula-
while (time queue is not empty) { tion consistency. The rule also applies to I T A devices con-
event +- GetNextEventO; nected to a given node and this expansion process is illus-
function c event.simulation-Mode; trated in Fig. 2. The lower levels of description are obtained
time t event.time; from the Oct database. Note that in Fig. 2(a), expansion is
data e event .simulation-Data; not required sincc both devices coonectcd to node Q are
1" Perform task associated with event "/ logic gates. However, in Fig. 2(b), two expansion steps arc
function ( data, time ); required before consistency is obtained. After the node
} assignments are completed, the set of ITA nodes are further
I* Produce output *I partitioned into subcircuits of tightly-coupled nodes as part
save-plot( ); of the standard I T A relaxation algorithm [SAL87]. Each
} ELogic node constitutes an ELogic subcircuit and each logic
node constitutes a Logic subcircuit.
The assignment phase is important because the program
schedules simulation functions based on the type of simula-
tion mode required by the subcircuit. Once the
partitioninglassignment phase is completed, each subcircuit
is simulated using the appropriate analysis mode during the
transient analysis.

5. MIXED-MODE INTERFACE
A major issue in all mixed-mode simulators is the inter-
facing of two or more simulation algorithms. Two problems
arise at the iiitcrface of two different modes of simulation:
signal mapping and evcnt scheduling. T h e use of an
Figure 1 : Using the "expand-down" command integrated simulation environment greatly simplifies the pro-
cessing requirements compared to the coinbineti-si/nulator
approach since the algorithms can he tailored specifically for
the mixed-mode application. For example, in iSI'LICE3, all
signals are representctl in terms their of real voltage values.
This includes the logic simulation mode which must be

13.1.2
 I T A subcircuit schedules its ELogic fanouts if its voltage
waveform has encountered an ELogic state during its last
voltage transition. This is consistent with the scheduling

f-
i s y used between ELogic subcircuits. Logic subcircuits also
schedule ELogic fanouts at each ELogic state along a transi-
tion of the logic waveform. Input source events follow simi-
lar rules as described above and are dependent on the types
of devices connected to them.
O n e additional complicating factor in inter-simulation
scheduling is due to rollbacks or step rejections. It may
occasionally be necessary to cancel a pending event or reject
a time-step and start reprocessing at an earlier time. When
this occurs, the scheduler must be backed up and the subcir-
cuits rescheduled and reprocessed accordingly. Initially, the
subcirciut which encountered the rejection is processed.
Then, its fanout subcircuits are scheduled and processed.
For efficiency, the fanouts simply compare their newly com-
puted solutions with previous solutions and only schedule
their fanouts if the new solutions are different from the old
Figure 2 : Automatic Expansion for Consistency solutions [SAL87]. Both ELogic and Logic schedule events
on fixed grid boundaries so that slight variations in the com-
puted schedule times are not inferred as different solutions.
This rollback strategy ensures that accurate solutions will be
modified slightly to accommodate this rule. Both I T A and obtained in an efficient manner.
Elogic already use voltage values in their calculations so this
requirement has no impact on them. Therefore, most of the 6. Mixed DC Solution Technique
signal mapping problems in the programs are resolved. iSPLICE3 uses a mixed-DC solution scheme to initial-
A second feature to resolve signal mapping problems is ize the circuit and processes the I T A and ELogic nodes
based on the devices connected to a given node. Logic gates using the standard Newton method. The efficiency of the
can be connected to the gate input of I T A or ELogic transis- Newton-Raphson method in terms of speed and convergence
tors, but cannot be connected to the drain or source termi- depends on the initial guesses of the node voltages provided
nals. If this is done by the designer, the logic gate is to it. iSPLICE3 attempts to generate a "good" initial guess
automatically expanded down to the appropriate level, as for the Newton method by employing switch-level analysis
described earlier and shown in Fig. 2(b). However, if a [BRY80]. Briefly, the entire circuit is first solved using zero
logic-level transistor is used in place of the electrical transis- delay switch-level logic simulation to derive the initial condi-
tor, no expansion is required. Elogic and I T A transistors tions at each node. Then, the standard Newton-Raphson
can be connected to one another in any manner since both method is applied to the non-Logic portions obtain the
modes use voltage, current and conductance information in correct solution. Since this technique usually provides an
their computations. initial guess that is close to the final solution, it ensures
T h e next issue is that of event scheduling between dif- proper and reliable convergence and reduces the total
ferent levels. O n e filtering operation that must be per- number of Newton-Raphson iterations. It has been found to
formed for I T A is to schedule only I T A fanout subcircuits be 4-5 times faster than the standard approach on digital cir-
during the iterative process, and schedule non-ITA fanouts cuits and has been incorporated as part of the mixed dc solu-
only when convergence occurs. This prevents non-ITA tion technique.
fanouts from unnecessarily being processed with partial solu- The X state deserves some special attention since all
tions during the iterations of I T A . A n ELogic subcircuit nodes are initialized to X as the first step of the switch-level
schedules its fanout subcircuits whenever the ELogic subcir- DC solution. iSPLICE3 processes the nodes from the inputs
cuit reaches a new voltage statz. A wakeup-call() event is to the outputs but if there are feedback paths in the network,
issued to I T A subcircuits from ELogic. That is, instead of some of the node values may be unknown (i.e., X) and this
scheduling the I T A events at the current time, it simply may result in the propagation of X's throughout the circuit.
schedules them when the other I T A subcircuits are already Obviously, this does not lead to a "useful" initial guess for
scheduled. This scheme prevents the overhead of reschedul- the Newton method. To avoid this problem, iSPLICE3
ing I T A subcircuits that already exist in the queue at some guesses the values of initial unknowns whenever required to
other time. Errors are controlled by the automatic time-step be either logic 0 or logic 1, depending on which one will shut
selection/rejection scheme of I T A . Note that if all I T A sub- off the feedback path. If an incorrect guess is made, the
circuits are latent, the fanout I T A subcircuits are scheduled feedback path will act to correct the situation later. This
normally at the current time. The same mechanism is used technique removes most of the X states at the output, partic-
when Logic schedules I T A except that ndeup-cnll()'s are ularly in troublesome circuits such as flip-flops. However,
issued along transitions of logic .vaveforms. some nodes may retain the X state if the correct state can
I T A subcircuits schedule their ELogic fanouts in the not be determined during the logic solution. These nodes
following way. After all I T A subcircuits have converged, an are reset to 0 V for NMOS and V,, for PMOS (rather than

13.1.3
VDD/2) since it places the transistors in the cutoff region of
operation rather than in the high-gain region.

7. MIXED-MODE SIMULATION EXAMPLE

The block diagram of a 64K CMOS Static Ram shown
in Fig. 3, containing 277 transistors, was simulated using
SPICE2 and iSPLICE3. It is comprised of row decoders,
column decoders, sense amplifiers, memory cells, etc., and
is therefore ideal as a mixed-mode simulation application. In
Table 1, the columns indicate the program name, the
number of electrical transistors, ELogic transistors, and
logic gates in the simulation and the total CPU-time.
I Program I Transistors I Gates I CPU-time I
Elec/I'TA ELogic sec.
SPICE2 277 0 0 10980
SPLICE3 277 0 0 1108

I SPLICE3 I 70 310 I
Table 1: Runtimes on Microvax-I1
As the results indicate, SPICE2 takes a long time for
this simulation whereas iSPLICE3 in I T A mode is already
approximately 10 times faster. A n overall improvement for
the mixed-mode simulation of 35x over SPICE2 was obtained
while producing comparable accuracy in the necessary por-

-
tions of the circuit as shown in the figure. A factor of 4x
over I T A was obtained in the full mixed-mode simulation
but, of course, roughly half of the circuit was simulated at I
the transistor level, so this is expected. 0- 300m'

Figure 3 : CMOS S R A M Block Diagram and Waveforms

8. CONCLUSIONS AND ACKNOWLEDGEMENTS
A new mixed-mode simulator, iSPLICE3, and its user CA., Nov. 1987.
interface, iSPI, have been described. The iSPLICE3 pro- [HAR86] D. Harrison, P. Moore, R . Spickelmier, A . R .
gram is written in C and runs under UNIX operating system. Newton, "Data Management and Graphics Editing i n the
The iSPI program is also written in C and is part of the Berkeley Design Environment", Proc. of ICCAD 1986.
Oct/VEM/RPC environment which requires X windows. [KIM841 Y. H. Kim, J . E. Kleckiier, R . A . Saleh, A . R .
These progams or a version of iSPLICE3 [SAL891 that Newton, "Electrical-Logic Simulation", Digest 1954 Int. Conf.
accepts standard textual input can be obtained from the on CAD, I E E E , Nov. 1984.
University of Illinois. [KLE84] J . E. Kleckner, "Advanced Mixed-Mode Simulation
The authors would like to thank Prof. A . Richard New- Techniques", P1i.D. dissertation, University of California,
ton for his encouragement and continuing support for this Berkeley, Memo No. UCB/ERL M84/48, June 1984.
work. J. Kleckner, K. Kundert, P. Moore, and J. White [NEW811 "Timing, Logic and Mixed-Mode Simulation for
contributed significantly to the current version of the pro- Large MOS Integrated Circuits", in Computer-Aids for
gram. Thanks also to R . Spickelmier and D. Harrison for VLSI Circuit, Sijthoff & Noordhoff International Publishers,
OctIVEMlRPC support. This research was supported by The Hague, pp. 175-239, 1981.
the Semiconductor Research Corporation and an NSF Fel- [PAG88] A . Pagones, "A Hierarchical Interface for Mixed-
lowship. Mode Simulation", M.S. Report, University of Illinois, 1988.
[SAKSO] K. Sakallah and S.W. Director, "An activity-
9. REFERENCES directed circuit simulation algorithm," Proc. IEEE Int. Conf.
[BRY80] R. E. Bryant, "An Algorithm for MOS Logic Simu- on Circ. and Computers, October 1980, pp.1032-1035.
lation", LAMBDA, 4th Quarter 1980, pp. 46-53. [SAL831 R . A . Saleh, J. E. Kleckner and A . R. Newton,
[CHE84] C. F. Chen and P. Subramaniam, "The Second "Iterated Timing Analysis and SPLICEl", I E E E Znt. Conf.
Generation MOTIS Timing Simulator- A n Efficient and on Computer-Aided Design, Santa Clara, C A . , 1983.
Accurate Approach for General MOS Circuits" Proc. 1984 [SAL871 R . Saleh, "Nonlinear Relaxation Algorithms for
lnt. S y i p . on Circ. and Sys., Montreal, Canada, May 1984. Circuit Simulation", P1i.D. dissertation, University of Cali-
[DER881 J. Dervenis, ' T h e Algorithms and Architecture of fornia, Berkeley, Memo No. UCH/EIIL, M87/21, April,
iSPLICE3", M.S. Report, University of Illinois, 1988. 1984.
[GR087] J. J. Grodstein, "SISYPHUS - An Environment [SAI.89] 11. Saleh et al., "iSPLICE3 User's Guide", Uiiiver-
for Simulation", Proc. Int. Conf. on C A D , Santa Clara, sity of Illinois, 1989.

13.1.4