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Published in IET Power Electronics

Received on 21st October 2007
Revised on 15th August 2008
doi: 10.1049/iet-pel:20070422

ISSN 1755-4535

Transformerless three-phase on-line UPS with

high performance
E.-H. Kim J.-M. Kwon B.-H. Kwon
Department of Electronic and Electrical Engineering, Pohang University of Science and Tech, Republic of Korea
E-mail: znight@postech.ac.kr

Abstract: A transformerless three-phase on-line uninterruptible power supply (UPS) is proposed. The proposed
UPS is composed of a rectier, an inverter and a battery charger/discharger. The rectier regulates a DC-link
voltage and performs power factor correction. On the other hand, the inverter provides a regulated sinusoidal
output voltage and has the current-limiting capability for an impulsive load. The battery charger/discharger
reduces the number of battery and supplies the power demanded by the load in the event of the input
power failure or abrupt decrease of the input voltage. Since both neutral lines of the input and output
voltages are connected at the centre of the DC-link, the need for an isolation transformer is eliminated and
the size, weight and cost of the system are signicantly reduced. Additionally, new control algorithms of the
rectier, the charger/discharger and the inverter are proposed.

1 Introduction converts the DC-link voltage into the output voltage with
PWM strategy. Therefore, the regulated sinusoidal output
With the increased dependence on the critical loads, such as voltage can be achieved. The battery which is connected in
computers, medical support systems and communication parallel with the DC-link capacitor is charged when the
systems, more priority will certainly be placed on supplying input voltage is in the normal condition and is discharged
continuous and disturbance-free power in the future. For when input power loss occurs. However, the conventional
these systems where it is impractical for the equipment UPS has several drawbacks. First, the high-voltage battery
manufacturer to provide built-in solutions to power-quality set has the problem associated with space, cost, reliability
problems, the user may nd the need for power interface and safety. Secondly, since the transformer is operated at
systems. The uninterruptible power supply (UPS) bridges line frequency, the transformer which weighs more than
the gap between equipment susceptibilities and power-line several tens kilograms increases the size, weight and cost of
disturbances and is designed to provide an alternate source the UPS and makes it difcult to move and install the
of conditioned, reliable, and seamless electrical power to UPS. To solve the above-mentioned problems, some kinds
the equipments. of the UPS have been presented in [9, 13, 14]. The
transformerless four-wire AC DC AC converter has been
In accordance with the topology or conguration, the UPS presented in [13]. Both the neutral points of the input and
can be classied as on-line, off-line and line-interactive types output are connected at the centre of DC-link capacitors to
[1 12]. The on-line UPS is generally preferred due to the eliminate a large and heavy transformer. In [14], the UPS
wide tolerance of the input voltage variation, the precise employ the separate charger/discharger to reduce the
regulation of output voltage and high reliability of the voltage of the battery set and the number of batteries.
system [1, 2]. A conventional three-phase on-line UPS However, the effort for performance improvement such as
consists of a rectier/charger, a battery set, an inverter, a increasing the back-up time and alleviating the adverse
transformer and bypass switches, as shown in Fig. 1. The effect on the output voltage is still necessary.
rectier performs power factor correction (PFC) with
pulse-width modulation (PWM) strategy and acts as a A three-phase on-line UPS in Fig. 2 is proposed in this
charger for the battery. On the other hand, the inverter paper. Both the neutral points of the input and output

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limiting the excessive current and quick recovery of the

output voltage is employed under the impulsive load.
Experimental results of a 10 kVA prototype show the
performance of the proposed UPS. The experimental
results indicate that the input and output characteristics
have a good steady-state performance and a good transient
response under the conditions such as the temporary loss of
input power and the step-load changes.

2 System description and

Figure 1 Conventional three-phase on-line UPS control scheme
Fig. 2 shows the conguration of the proposed on-line UPS.
sources are connected at the centre of DC-link capacitors to The proposed UPS is composed of a rectier, a charger/
ensure a proper bypass-mode operation without utilising a discharger, an inverter and transfer switches. To balance
transformer. By utilising the separate charger/discharger, two DC-link capacitor voltages, the proposed UPS includes
the voltage of the battery set is lowered and the number of an auxiliary circuit which consists of a leg and an inductor
batteries is reduced. Therefore, the problem associated with although it is not depicted for the simplicity. The UPS has
the size, weight and installation can be solved with a three modes: normal mode, back-up mode and bypass
reasonable cost. To ensure the proper operation of the UPS mode. In the normal and back-up modes, the thyristor S15 ,
and to minimise adverse effects of the input and output S16 , S17 are off-state and S18 , S19 , S20 are on-state,
disturbance, new control algorithms of the rectier, the respectively. Thus, the power can be transferred through
charger/discharger and the inverter are proposed. A new the inverter. In the event of an internal malfunction of the
adaptive gain controller decreases the DC-link voltage UPS or an overload of the inverter, the bypass mode is
variation at step-load changes and an employed mode- started. In the bypass mode, the thyristor S15 , S16 , S17 are
change method increases the back-up time, respectively. on-state and S18 , S19 , S20 are off-state, respectively. The
When the impulsive loads such as rectier loads, no-load power demanded by the load is directly supplied from the
transformer and electric motor are attached, an excessive AC input source. Three parts, which are the rectier, the
load current caused by low impedance during the transient charger/discharger and the inverter, are independently
status may greatly endanger the systems [15]. To overcome controlled with PWM strategy. Three-phase AC input
this problem, a new technique which is characterised by voltages vrn , vsn and vtn are connected to the rectier

Figure 2 Overall block diagram of the proposed three-phase on-line UPS

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through a magnetic contactor (MC). The MC is closed which is composed of the nominal duty Dn and the
whereas the rectier is operating. The rectier regulates the controlled duty Dc . Then, Dn and Dc are represented as
voltage across the DC-link capacitors Cd1 and Cd2 and
performs PFC in the normal mode. In the normal or back- Vrn
up mode, the inverter provides three sinusoidal output Dn 0:5 sin vt
Vd
voltages vun , vvn and vwn . In order to achieve no transition (5)
time at the moment of mode change from normal to L
Dc  i Dir
bypass, each inverter output voltage vun , vvn and vwn is V d Ts
synchronised with vrn , vsn and vtn , respectively. With
normal DC-link voltage, the battery charger/discharger is where Vrn is a peak value of vrn and sin vt is a sine value
operated as a buck converter which supplies the energy into obtained from PLL, respectively. To force the current ir
the battery set. When the DC-link voltage is of the rectier to track its current command ir , a
instantaneously decreased, the battery charger/discharger is proportional and integral (PI) current controller is utilised
operated as a boost converter which steps up the battery as follows
voltage to the DC-link voltage.

Dc kp (ir  ir ) ki (ir  ir )dt (6)
2.1 Rectier control
The rectier with the three-phase input in Fig. 2 can be
From (5), it can be seen that the proportional gain kp is
considered as three single-phase half-bridge rectiers
2L/VdTs . The output Dc of the current controller only
operating in parallel. When the input source goes into the
generates the inductor voltage drop required to maintain
preset working range and the synchronism of phase-locked
the sinusoidal input current. With the addition of the
loop (PLL) is achieved, MC is closed and the rectier
nominal duty Dn to the rectier, which is originally a
starts to perform the unity power factor control. The
nonlinear dynamic system, the relation between Dc and ir
analysis for an r-phase input voltage vrn is described, since
becomes a rst-order linear dynamic system (5) with easy
the analyses for the others are analogous.
controllability. Thus, the addition of Dn relaxes the
burden of the current controller and improves the input
Two switches of each leg are driven complementarily with
current waveform.
PWM strategy. In practice, both switches are off-state during
a short dead time to avoid short circuiting of the DC-link.
The block diagram for the control of the rectier is shown
While the switch S1 is on-state, the voltage equation of the
in Fig. 3. The control strategy for the rectier uses multiple
boost inductor Li is obtained as
control loops for each leg. One is an outer voltage loop and
the other is an inner current loop. The DC-link voltage is
Vd d regulated by a slow outer loop and the input current is
vrn  Li ir (1)
2 dt controlled by a much faster inner loop to provide a good
input power factor. To force the DC-link voltage to track
where ir and Vd are the r-phase input current and the DC- its voltage command Vd_pfc , the voltage controller utilises a
link voltage, respectively. Similarly, while S1 is off-state, the conventional PI controller as follows
following voltage equation is satised
Ir kp (Vd (7)
pfcVd )ki (Vd pfc Vd ) dt
Vd d
vrn Li ir (2)
2 dt When the input power is lost, MC is opened and the rectier
is disabled. The power demanded by the load is supplied
Depending on S1s duty ratio DS1 , the average inductor from the battery set.
voltage over a switching period Ts gives the input current
variation Dir as follows
2.2 Battery charger/discharger control
   
Vd Vd   Di If the rectier can provide enough power to supply the output
vrn  DS1 vrn 1  DS1 Li r (3)
2 2 Ts power, then the charger/discharger in Fig. 2 is operated in a
charging mode, otherwise the charger/discharger is operated
in a discharging mode. In the charging mode, the charger/
Therefore, DS1 is obtained as discharger is operated as a conventional buck converter
and the switch S8 of the battery charger/discharger is
consistently turned off. It is assumed that the inductor
vrn L current ibat ows continuously. While the switch S7 is on-
DS1 Dn Dc 0:5  i Dir (4)
Vd Vd Ts state, the voltage equation of the inductor Lbat is obtained

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Figure 3 Control scheme for the rectier

as follows Fig. 4a shows the control algorithms in the charging mode.

To obtain the desired battery voltage and capacity, the
dibat battery set is made up of some cells which are electrically
Vbat  Vd Lbat (8)
dt connected in series or a combination of series and parallel.
Since the battery set should be charged at a specic
where Vbat is the voltage across the battery set. On the other charging rate until the battery voltage reaches a given end-
hand, while the switch S7 is off-state, ibat is freewheeling of-charge voltage or a oating voltage, the battery charger
through the body diode of S8 . Thus, the following voltage has to be able to limit the charging current to the given
equation is satised rated battery current Ichrg_limit . When the battery voltage is
lower than the oating voltage, the output of the voltage
dibat controller is limited to the given rated battery current.
Vbat Lbat (9)
dt Once the battery voltage reaches the oating voltage, the
battery current decreases slowly and the battery voltage is
Therefore, the average inductor voltage over Ts gives the controlled at the oating voltage.
battery current variation Dibat as follows
When the rectier becomes unavailable or the current
Di required by the load exceeds the output rating of the
(Vbat  Vd )DS7 Vbat (1  DS7 ) Lbat bat (10)
Ts

Therefore, DS7 is obtained as follows

Vbat Lbat Dibat

DS7 Dn Dc  (11)
Vd Vd Ts

The nominal duty Dn and the controlled duty Dc are

represented as

Vbat Lbat
Dn , Dc Di (12)
Vd Vd Ts chrg

where the charging current ichrg is 2ibat . To force ichrg to

track its command ichrg , the current controller is utilised as
follows
    Figure 4 Control scheme of the battery charger/discharger
  a Control scheme of the battery charger
Dc kp ichrg  ichrg ki ichrg  ichrg dt (13)
b Control scheme of the battery discharger

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rectier, the battery supplies the load power. In the

discharging mode, the switch S7 of the charger/discharger
is consistently turned off and the charger/discharger is
operated as a conventional boost converter. Fig. 4b shows
the control algorithm in the discharging mode. Assuming
that the inductor current ows continuously, the average
inductor voltage over Ts gives the battery current variation
Dibat as follows

Dibat
Vbat DS8 (Vbat  Vd )(1  DS8 ) Lbat (14)
Ts

The S8s duty ratio DS8 is obtained as follows

Vbat Lbat Dibat

DS8 Dn Dc 1  (15)
Vd V d Ts

To force Vd to track the voltage command Vd_dchg , the voltage

controller is utilised as the PI controller and provides the
current command ibat . The current controller which is
utilised as the PI controller generates the controlled duty Figure 5 Control scheme of the inverter
Dc such as (13).

current will ow until the capacitor of the load is fully

2.3 Inverter control charged. This high current is adverse to the switching devices
The inverter with three-phase output can be considered as in the inverter. If the inverter output voltage is forced to have
three single-phase half-bridge inverters as shown in Fig. 5. smaller amplitude, then it is possible to limit the power
The u-phase analysis is described, since the analyses for the delivered to the load. International electrotechnical
others are analogous. The u-phase operation of the inverter commission (IEC) has established a standard IEC 62040-3
is divided into two modes according to the absolute concerning the method of specifying the performance and test
value of an output current jiuj. When the absolute value of requirements [16, 17]. According to IEC 62040-3, the
the output current jiuj is lower than the current limit nonlinear load as shown in Fig. 6 is tested for impulsive
value, the inverter is operated in the normal mode. In the loading. The values of the lter capacitor Cf , the series line
normal mode, the duty ratio of the inverter switch S9 is resistor Rs and the load resistor RL can be calculated
determined as according to the IEC 62040-3 guideline.

Vd pfc
DS9 0:5 m  sin ref (16) To comply with IEC 62040-3, a new inverter control
Vd technique for impulsive loading is proposed. Similar to the
normal mode of the inverter, the u-phase analysis is
where m is the output of the PI voltage controller and sin_ref described. Before the capacitive rectier in Fig. 6 is
is sin vt obtained from PLL. If the input AC source is within attached to the inverter, the voltage across Cf is zero. When
a preset tolerance, then sin vt is synchronised with its the capacitive rectier is attached to the inverter, the initial
corresponding input voltage vrn in order to transfer power short-circuit current can exceed the current-limit value,
to the load without a break when the UPS enters the
bypass mode. To reduce adverse effects from the DC-link
voltage ripple, (16) includes the feed-forward term Vd
which can be immediately obtained by A/D conversion.
Since the feed-forward control of Vd is faster than PI
control of m, it improves a transient response of the output
voltage for DC-link voltage variation occurred at step-load
change or at outage of the input source.

Various loads such as linear, nonlinear, single-phase or three-

phase loads and so on can be attached at the output of the
inverter. The nonlinear load such as a capacitive rectier in
Fig. 6 may be the worst case of the loads. When the capacitive
rectier is attached to the inverter, the inverter of the UPS
will deliver excessive current because the large charging Figure 6 Test circuit of impulsive loading

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since Rs is a very small value. A large transient current spike limit level. At some degree of the next half period, the
may occur due to the stored energy in the output lter output current jioj is detected between CL and OC and
capacitor Co of the inverter. However, it is not necessary to the present value of sin_ref is stored to sin_limit. Until
protect this peak short-circuit current, since the duration of sin_limit is greater than sin_ref, the output current is
the initial transient is very short. Once the stored energy in controlled near CL and the capacitor of the load is charged
Co is dissipated, the large charging current will ow from to some degree. The above process is repeated several half
the inverter until Cf is fully charged. This high current periods. When the capacitor of load is fully charged in
adversely affects to the switching devices in the inverter. If some cycles, no further impulsive current ows through the
the amplitude of the output voltage is forced to be near the inverter, and the inverter is operated in the normal mode.
voltage of Cf , then it is possible to limit the current owing The output voltage is recovered to its rated value. The
into the load. To limit this excessive current, the inverter advantage of this scheme is that it can be implemented
enters into a current limit mode when jiuj is greater than with a software program without an additional hardware.
the current limit level (CL). The duty of inverter switches In addition, it has an adjusting ability for different
in the current limit mode is determined in a different way nonlinear loads such as strong or weak, long or short
from the normal mode. The value of sin_ref is sin vt in impulsive loads.
normal mode. However, in the current limit mode, it is
modied to limit the amplitude of the output current 2.4 Adaptive gain control of the rectier
under CL and the output waveform is deformed. The
detailed algorithm for the proposed current limiter is
and the discharger
explained in the owchart shown in Fig. 7. When the The block diagram for the control of the rectier is shown in
capacitive load is attached, a large current spike over the Fig. 3. The DC-link voltage is regulated by slow voltage
over current level (OC) is detected since the stored energy controller whereas the current controller that shapes the
in Co is dissipated. At the moment, the mode of the input current is much faster resulting in a good input
inverter goes into the current limit mode and sin_limit power factor. If both the three-phase input currents and
becomes zero. Until the polarity of the output voltage is the output currents of UPS are sinusoidal and balanced, the
changed, the output current is controlled near the current input and output powers of the UPS are equal and

Figure 7 Flowchart of the current-limiter of the inverter

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constant. Therefore, the DC-link voltage does not have the 2.5 Operation principle of mode change
voltage ripple. However, under the real load conditions, the
output currents are usually neither sinusoidal nor balanced, In the conventional UPS shown in Fig. 1, the battery set is
and the DC-link capacitors may have voltage ripples due to automatically discharged and the DC-link voltage is kept
the input and output power difference of the UPS. within small variation when the input power is lost.
Therefore, the voltage controller of the rectier has to be However, in the proposed converter, the charger/discharger
designed to ensure that the input current command is not has to immediately start to discharge the battery set to keep
affected by this low frequency harmonic ripple. In a the DC-link voltage Vd when the input power is lost.
conventional PI voltage controller, the voltage controller is
designed slowly with small proportional gain kp in order to Due to the need of a strategy to keep the DC-link voltage,
minimise adverse effects on the input current command. the proposed UPS utilises a mode-change method as shown
However, small kp usually results in unacceptable variation in Fig. 9. A detailed description of the mode-change method
of DC-link voltage at step-load change from no load to full is as follows. Three parts, which are the rectier, the charger/
load or vice versa. If ki is very small and can be neglected, discharger and the inverter, are controlled independently and
(7) shows that the magnitude of the DC-link voltage only the DC-link voltage information is shared commonly.
variation at step-load change is about Ir,max/kp where Ir,max When the AC input voltage is within the preset tolerance,
is the peak of r-phase input current at full load. A new the UPS operates in the normal mode. The rectier boosts
control algorithm is proposed to solve this problem. To the three-phase input voltages into the DC-link voltage Vd
force Vd to track its command Vd_pfc , an adaptive gain with PFC function and the inverter converts Vd into the
controller is utilised as follows three-phase sinusoidal output voltages. Since an output
neutral point N is connected at the centre of DC-link
capacitors, Vd has to be higher than 2Vun where Vun is a

peak value of vun . If the rectier can provide enough power
Ir kp (Vd )(Vd pfc  V d ) ki (Vd )(Vd pfc  Vd )dt
to supply the output power, then the DC-link voltage is
controlled at the voltage command of the rectier Vd_pfc
(k1 k2 jVd pfc  Vd ja )(Vd pfc  Vd ) (17) and the charger/discharger operates as a battery charger as

shown in Fig. 9. If the current required by the load exceeds
ki (Vd )(Vd pfc  Vd )dt the output rating of the rectier due to the outage or sag of
input voltage, then the rectier becomes unavailable or
the input currents of the rectier are limited. In this case,
where kp(Vd) and ki (Vd) are functions of Vd , and k1 , k2 and a the DC-link voltage goes down and the charging current of
are constant values. As shown in Fig. 8, when the voltage
error (Vd_pfc 2 Vd) is smaller than conventional one, the
gain kp(Vd) is small to improve steady-state performance,
whereas, when the voltage error (Vd_pfc 2 Vd) is large,
kp(Vd) is larger to improve dynamic performance and to
reduce DC-link voltage variation at step-load change. In a
similar manner, the adaptive gain controller can be applied
to the integral gain to track DC-link voltage command
quickly. Experimental results show that the proposed
adaptive controller reduces the DC-link voltage variation at
step-load changes by more than 50% without adverse
effects on input current command at steady-state.

Figure 8 Comparison of proportional gain values with Figure 9 Mode-change method of the battery charger/
respect to voltage error discharger

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the battery set decreases. Once Vd arrives at a starting voltage Table 1 System parameters of the prototype
of discharging Vd_start , the rectier/charger immediately
starts to operate as the discharger and supplies a part or all Parameters Symbol Value
of the load power instead of the rectier. The DC-link rated battery voltage Vbat 384 V
voltage is regulated to be the output voltage command of
the battery discharger Vd_dchg which is slightly lower than DC-link voltage reference of the Vd_pfc 700 V
Vd_pfc as shown in Fig. 9. When the input voltage returns rectier
to within the preset voltage tolerance and the current DC-link voltage reference of the Vd_dchg 693 V
required by the load is lower than the output rating of the discharger
rectier, the DC-link voltage goes up to Vd_pfc and the
duty of the discharger DS8 decreases and reaches to zero starting voltage of the discharger Vd_start 655 V
since Vd_dchg is lower than Vd_pfc . Once DS8 becomes zero, output current limit level CL 50 A
the charger/discharger operates as the charger, which
transfers the energy to the battery set. line frequency f 60 Hz
boost inductor of the rectier Li 0.8 mH
In case of the input voltage sag, the power required by the
load is supplied by the both the input power and the battery buck/boost inductor of the battery Lbat 1 mH
power as shown in Fig. 9. The utilisation of the input power charger/discharger
is enhanced and the use of the battery power is minimised. output lter inductor Lo 0.8 mH
Therefore, the back-up time is effectively increased.
Moreover, since the DC-link voltage is immediately DC-link capacitor Cd1 ,Cd2 4700 mF
compensated by changing the operation mode of the output lter capacitor Co 50 mF
battery charger/discharger, the transient effect of the
output voltage is minimised and uninterrupted power is
supplied to the load irrespective of the line condition.

3 Experimental results
In a microprocessor-based control system, software exibility
facilitates the development and updating of the control
technique and uses control theory to obtain high
performance. Moreover, the single-chip microcontroller can
implement the controller with lower cost and smaller size
than a general-purpose microprocessor with accompanying
external circuits such as an external memory, an A/D
converter, a D/A converter and a PWM generator. The
hardware circuit of the proposed UPS in Fig. 2 was
implemented using a single-chip microcontroller. It is
divided into two parts: a controller circuit and a power
circuit. The controller part includes a single microcontroller
dsPIC30F6015 (Microchip) which is capable of running
the control algorithms and driving the control circuits in
real time. Voltage and current signals are measured by
using 10-bit A/D converter in the microcontroller. The
implementation of the voltage or current controllers and
PWM pulse generation is performed at every sample period
of 100 ms.

The major components and parameters of the hardware

circuit used for experiments are presented in Table 1. The
UPS is tested over the 380 V line-to-line input and output
voltages and the switching frequencies of the rectier, the
charger/discharger and the inverter are selected as 15 kHz.
The output power of the UPS is specied as 10 kVA.
Figure 10 Major waveforms at the outage and sag of the
Fig. 10a shows major waveforms at the failure of the input input source
source. As shown in Fig. 10a, the input current is in phase a Waveforms at the outage
with the input voltage and its waveform is nearly sinusoidal b Waveforms at the sag

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before the loss of the input power. The input current

produces a power factor of 0.99, and its THD is measured
at 3.5%. When the input power is lost, Vd is decreased.
Once Vd reaches Vd_start , the mode of the charger/
discharger is immediately changed from the charging mode
to the discharging mode. Since the DC-link voltage ripple
is rapidly compensated by the feed-forward term of the
inverter controller and the DC-link voltage is kept over the
doubled peak value of the output voltage, the transient
effect of the output voltage is negligible and the UPS
transfers seamless power to the load. Fig. 10b shows major
waveforms at the sag of the input source. As shown in
Fig. 10b, both the rectier and the discharger provide the
power to the load to enhance the utilisation of the input Figure 12 Output voltage and current under impulsive load
power. Therefore, the battery backup time is effectively for vun
increased.
negligible at step-load change. By employing the proposed
Fig. 11 shows the DC-link voltage responses at step-load adaptive gain controller in (17) of the rectier, the DC-link
change from no load to full load and vice versa. Since the voltage variation is reduced over 50% compared with that
frequent mode changes of the charger/discharger reduce in the conventional PI controller.
the battery back-up time, the DC-link voltage Vd has to be
kept over Vd_start in the normal mode when the output load Fig. 12 shows the output voltage and current waveforms
changes from no load to full load. Experimental results under the impulsive load. When the capacitive rectier load
show that Vd is always higher than Vd_start in the normal (Cf 4700 mF, Rs 0.5 V, RL 28 V) is connected to
mode and the transient effect on the output voltage is the output voltage vun , the UPS can full the impulsive
loading quickly. In addition, vun is recovered to the rated
voltage within two cycles of the fundamental line period.
Since three outputs of the inverter are controlled
independently, the impulsive loading for vun does not affect
the waveforms of vvn and vwn . Since the proposed current
limit algorithm is fully implemented in software, the cost is
reduced.

4 Conclusions
The three-phase transformerless on-line UPS has
been proposed. Since the proposed UPS is implemented
without an isolation transformer, the size, weight and cost
of the system are signicantly reduced. The inverter is
independently operated regardless of the line condition and
the UPS transfers uninterrupted power to the load. In case
of the abrupt decrease of the input voltage, a mode-change
method of the charger/discharger enhances the utilisation
of the input power and improves the dynamic response of
the output voltage. Also, the experimental results show that
the proposed current-limiting technique has good current-
limiting characteristics for the impulsive loads. In addition,
the proposed UPS has good dynamic and steady-state
performance.

5 References
[1] BEKIAROV S.B., EMADI A.: Uninterruptible power supplies:
classication, operation, dynamics, and control. IEEE
Figure 11 Experimental waveforms under step-load change APEC02, 2002, vol. 1, pp. 597 604
a Load step response from 100 to 0%
b Load step response from 0 to 100% [2] KARVE S.: Three of a kind, IEE Rev., 2000, 46, pp. 27 31

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doi: 10.1049/iet-pel:20070422 & The Institution of Engineering and Technology 2009
www.ietdl.org

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