..

,. ANALOG
W DEVICES
IntegratedCircuit
PrecisionInstrumentation
Amplifier
[ AD521 I

FEATURES PIN CONFIGURATION

Programmable Gains from 0.1 to 1000
Differential Inputs + INPUT I 1 141 ~AIN
High CMRR: 11OdBmin
Low Drift: 2p.Vfc max (L) GAI~ 12 131 ~ALE
Complete Input Protection, Power ON and Power OFF
Functionally Complete with the Addition of Two Resistors
Internally Compensated
Gain Bandwidth Product: 4OMHz OFFSET
TRIMI 4
Output Current Limited: 25mA

a
Very LowNoise: 05p.V p-p, 0.1Hzto 10Hz, RTI (I G -1000
Chips are Available
OFFSET
TRIMI 8 9 I COMPo

Not
Reco OUTPUT I 7 81 v+

PRODUCT DESCRIPTION mme +70°C.The "S" grade guarantees performance to specification

nded
The AD521 is a second generation, low cost, monolithic IC
instrUmentation amplifier developed by Analog Devices.As a
over the eXtended temperatUre range: -SSoC to +125°C.
PRODUCT HIGHLIGHTS
trUe instrUmentation amplifier, the AD521 is a gain block with
differential inputs and an accurately programmable input/ for n
1. The ADS21 is a trUe instrumentation amplifier in integrated

ew D
circuit form, offering the user performance comparable to
output gain relationship. many modular instrumentation amplifiers at a fraction of
the cost.
The AD521 IC instrUmentation amplifier should not be con-
fused with an operational amplifier, although several manu-
esig
2. The AD521 has low guaranteed input offset voltage drift
factUrers(including Analog Devices)offer op amps which can
be used as building blocks in variable gain instrumentation
amplifier circuits. Op amps are general-purpose components
applications. ns
(21lVf C for L grade) and low noise for precision, high gain

which, when used with precision-matched external resistors, 3. The AD521 is functionally complete with the addition of
can perform the instrUmentation amplifier function. two resistors. Gain can be preset from 0.1 to more than
1000.
An instrumentation amplifier is a precision differential volt-
age gain device optimized for operation in a real world envi- 4. The AD521 is fully protected for input levelsup to 15V
ronment, and is intended to be used wherever acquisition of a beyond the supply voltages and JOV differential at the
useful signal is difficult. It is characterized by high input im- inputs.
pedance, balanced differential inputs, low bias currents and 5. Internally compensated for all gains, the AD521 also offers
high CMR. the user the provision for limiting bandwidth.
As a complete instrUmentation amplifier, the AD521 requires 6. Offset nulling can be achieved with an optional trim pot.
only two resistors to set its gain to any value between 0.1 and 7. The AD521 offers superior dynamic performance with a
1000. The ratio matching of these resistors does not affect the gain-bandwidth product of 40MHz, full peak response of
high CMRR (up to 120dB) or the high input impedance (3 X 100kHz (independent of gain) and a settling time of 5p.s
109il) of the AD521. Furthermore, unlike most operational to 0.1% of a 10V step.
amplifier-based instrUmentation amplifiers, the inputs are
protected against overvoltagesup to :1:15volts beyond the
supplies.
The AD521 IC instrumentation amplifier is available in four
different versions of accuracy and operating temperatUre range.
The economical "J" grade, the low drift "K" grade, and the
lower drift, higher linearity "L" grade are specified from 0 to

01::\/ 1\
-~ ~-- ~_. ~
 AD521-SPECIFICATIONS
(typical @ Vs = :t15V, RL= 2kO and TA = +25°Cunlessotherwisespecified)
AD521SD
~ AD521JD AD521KD AD5HW (AD5HSDI883B)
GAIN
Ra..e (For Spocified Operation, Note I) I to 1000
Equation G. Rs/RC V/V
Error from Equation (to.25~.004G)%
Nonlin..rity (NatO 2)
I..G<IOOO
Gain Temporaturo C""fficient
0.2% max
t(3 to.05G)f£mtC
.
0.1% max
t(l5 to.4G)f£mtc
OUTPUT CHARACTERISTICS
RatOd Output UOV, tlOmA min
Output at Maximum Oporati.. Temporaturo tlOV @ SmA min
Impodance 0.10
DYNAMIC RESPONSE
Small Signal Bandwidth (13dB)
G=I >2MHz
G= 10 300kHz
G= 100 200kHz
G = 1000 40kHz
Small Signal, t1.0% Flatn..s
G=I 75kHz
G= 10 26kHz
G= 100 24kHz
G = 1000 6kHz
Full Peak Response (NatO 3) 100kHz
Skw RatO, I..G ..1000 10V/lis
Settling Time (any 10V stOp to within 10mV of Final Value)
G-I 711'

Not
G= 10 511S
G. 100 lOlls
G.lOOO 35l1s

Reco
DifforcntiaJ Overload Recovery (130V Input to within
10mV of Final Value) (NatO 4)
G - 1000

mme
SOliS
Common Mode StOp Recovery (30V Input to within
10mV of Final Value) (NatO 5)
=1000
nded
G lOllS
VOLTAGE OFFSET (may be nulled)
Input Offset Voltage (Vas,) 3mV max (2mV typ) l.5mV max (0.5mV ryp) l.Omv max (0.5mV typ)

fo. r n .
vs. Temporature 1511VtC max (7I1VtC typ) 511VtC max (l.5I1Vfc typ) 2IIV/.C max
vs. Supply 311V/%
Output Offset Voltage (Vaso) 4OOmV max (200mV typ) 200mV max (30mV typ) lOOmV max
vs. Temporature
vs. Supply (Narc 6)
4OOIIVtCmax (l50IlV!':C typ)
0.005VOSO/%
ew . D
150llVfc max (50IlV!':C typ) 7511VtCmax

esig
INPUT CURRENTS
Input Bias Current (either input) 80nA max 4OnA max

.
ns
vs. Temporature InAtC max 500pAfC max
vs. Supply 2 %IV
Input Offser Current 20nA max 10nA max
vs. Temporature 250pAtC max 125pAtC max
INPUT
Differential Input Impodance (NatO 7) 3 x 1O911111.8pF
Common Mode Input Impedance (NatO 8) 6 x lO'O11113.0pF
Input Voltage Range for Specified Poriorrnance
(with rospect to ground) tlOV
Maximum Voltage without Damage to Unit, Power ON
or OFF Differential Mode (Note 9) 30V
Voltage at either input (Narc 9) Vs tl5V
Common Mode Rejection Ratio, DC to 60Hz with IH1
source unbalance
Gol 70dB min (74dB typ) 74dB min (80dB typ)
GolO 90dB min (94dB typ) 94dB min (lOOdB typ)

NOISE
GolOO
G . 1000
lOOdB min (l04dB typ)
lOOdB min (lIOdB typ)
1O4dB min (l14dB typ)
llOdB min (l20dB trP,) -
-
Voltage RTO (p-p)@O.IHz to 10Hz (Narc 10)
RMS RTO, 10Hz to 10kHz
Input Current, rms, 10Hz to 10kHz
REFERENCE TERMINAL
Bias Current

-
311A
Input Resistance IOM11
Voltage Range tlOV

-
Gain to Output I
POWER SUPPLY
Oporati!ll Voltage Ra..e t5V to U8V
Quincent Supply Current SmA max
TEMPERATURE RANGE
Spooned Performance 0 to +70.C -55.Cto+125.C
Oporating -25.C to +85.C
Storage

°Specificatiom AD521JD.
-65.C to +150.C
--
-55.C to +125.C

ooSpec:if'ocatioaa AD5Z1KD.
Specificatioaaoubjoct10 <!wit< without DOO«.

--- -- - --------
REV.A ~
 [ Applying
the AD521
NOTES: mon mode signal greater than Vs -o.5V is applied to the
1. Gains below 1 and above 1000 are obtained by simply ad- inputs, transistor clamps are activated which drop the excessive
justing the gain setting resistors. (Input voltage should be re- input voltage across internal input resistors. Power dissipated
stricted to :t10V for gains equal to or less than 1.) in these resistors causes temperatUre gradients and a correspon-
ding change in offset voltage, as well as an added thermal time
2. Nonlinearity is defined as the ratio of the deviation from
constant, but will not damage the device.)
the "best straight line" through a full scale output range of
1:9volts. With a combination of high gain and :tlO volt output 6. Output Offset Voltage versus Power Supply includes a
swing, distortion may increase to as much as 0.3%. constant 0.005 times the unnulled output offset per percent
change in either power supply. If the output offset is nulled,
3. Full Peak Response is the frequency below which a typical
the output offset change versus supply change is substantially
amplifier will produce full output swing. reduced.
4. Differential Overload Recovery is the time it takes the ampli- 7. Differential Input Impedance is the impedance between the
fier to recover from a pulsed 30V differential input with 15V two inputs.
of common mode voltage, to within 10mV of final value. The
test input is a 30V, 10,us pulse at a 1kHz rate. (When a differ- 8. Common Mode Input Impedance is the impedance from
ential signal of greater than 11V is applied between the inputs, either input to the power supplies.
transistor clamps are activated which drop the exces!' input
voltage across internal input resistors. If a continuous overload

Not
is maintained, power dissipated in these resistors causes temper-
atUre gradients and a corresponding change in offset voltage,
9. Maximum Input Voltage (differential or at either input) is
30V when using :t15V supplies. A more general specification is
that neither input may exceed either supply (even when
Vs = 0) by more than 15V and that the difference between the
a
Reco
as well as added thermal time constant, but will not damage
the device.)
two inputs must not exceed 30V. (See also Notes 4 and 5.)

mme
5. Common Mode Step Recovery is the time it takes the amp-
10. O.lHz to 10Hz Peak-to-Peak Voltage Noise is defined as
the maximum peak-to-peak voltage noise ovserved during 2
lifier to recover from a 30V common mode input with zero
nded
volts of differential signal to within 10mV of final value. The
of 3 separate 10 second periods with the test circuit of Fig-
ure 8.
test input is 30V, 10,us pulse at a 1kHz rate. (When a com-
for n
ew D
ORDERING GUIDE METALIZATION
esig
PHOTOGRAPH
Dimensions shown in inches and (mm).

Model
AD52lJD
Temperature
Range
DoC to + 7DoC
Description
14-Pin Ceramic DIP
Package
Option!
D-14
Contact factory for latest dimensions.
ns
AD52IKD DoC to + 7DoC 14-Pin Ceramic DIP D-14
AD521LD DoC to + 7DoC 14-Pin Ceramic DIP D-14
AD521SD - 55°C to + 125°C 14-Pin Ceramic DIP D-14
AD521SD/883B2 - 55°C to + 125°C 14-Pin Ceramic DIP D-14
AD52lJ Chips DoC to + 7DoC Die
AD521K Chips DoC to + 7DoC Die
AD521S Chips - 55°C to + 125°C Die
NOTES
14
IFor outline information see Package Information section. RGAIN
2Standard military drawing available.
1
+INPUT

~
R GAIN
2 3
-INPUT

0.110 {2.8001
4
OFFSET
TRIM
5
-Vs
6
OFFSET
TRIM

8BLA fN~TRf !MFNTA TfnN AMP! !FfFR.C; 4-,ffl;

 AD521
DESIGN PRINCIPLE
Figure 1 is a simplified schematic of the AD521. A differential 4. Do not exceed the allowable input signal range. The line-
input voltage, VIN,appears across RG causing an imbalance in arity of the ADS21 decreases if the inputs are drivenwithin
the currents through Ql and <l2,~I=VIN/RG' That imbalance 5 volts of the supply rails, particularly when the deviceis
is forced to flow in Rs because the collector currents of Q3 used at a gain less than 1. To avoidthis possibility,atten-
and <4 are constrained to be equal by their biasing (current uate the input signal through a resistive divider networkand
mirror). These conditions can only be satisfied if the differen- use the ADS21 as a buffer, as shown in Figure 4. The resis-
tial voltage across Rs (and hence the output voltage of the tor R/2 matches the impedance seen by both AD521 in-
AD521) is equal to ~I X Rs. The feedback amplifier, ApB puts so that the voltage offset caused by bias currents will
be minimized.
performs that function. Therefore, VOUT= V~ X Rs or 5. Use the compensation pin (pin 9) and the applicable com-
VOUT - Rs
VIN ~ - +V
pensation circuit when the amplifier is required to drive a
capacitive load. It is worth mentioning that coaxial cables
can '~invisibly" provide such capacitance since many popu-
lar coaxial cables display capacitance in the vicinity of 3OpF
VON
I-IrQ
per foot.
This compensation (bandwidth control) feature permits the
VOUT V,N
user to fit the response of the AD521 to the particular appli-
"'RI. 1IQ cation as illustrated by Figure S. In cases of extremely high

Not OR-VOUT.,,"
v-. Ira load capacitance the compensation circuit may be changed

Reco
as follows:
1. Reduce 680n to 24n

mme SENSE 2.
3.
Reduce BOn to 7.5n
Increase 1000pF to O.IJ,LF

nded 4. Set Cx to 1000pF if no compensation was originally

used. Otherwise, do not alter the original value.

t'x t for n
This allows stable operation for load capacitances up to
.'
ew D
IX
'i ~~, 3000pF, but limits the slew rate to approximately 0.16VIJ,Ls;
CURRENT MIRROR

V-
esig
6. Signals having frequency components above the Instrumen-
tation Amplifier's output amplifier closed-loop bandwidth
Figure 7. Simplified AD527 Schematic

APPLICATION NOTES FOR THE AD521

will be transmitted from V- to the output
attenuation. Therefore, it is advisable to decouple the V-
supply line to the output common or to pin 11.1
ns
with little or no

These notes ensure the AD521 will achieve the high level of
V+
performance necessary for many diversified IA applications.
1. Gains below 1 are realized by adjusting the gain setting
resistors as shown in Figure 2 (the resistor, as betWeen
+IN
pins 10 and 13 should remain 100kn :1:15%,see application
note 3). For best results, the input voltage should be re-
OUTPUT
stricted to :tl0V even though the gain may be less than 1.
See Figure 6 for gains above 1000.
-IN OUTPUT
2. Provide a return path to ground for input bias currents. The SIGNAL
COMMON GAIN VALUE OF RO
AD521 is an instrumentation amplifier, not an isolation
0.1 1I0Il1
amplifier. When using a thermocouple or other "floating" 1 1(JOkS1
10 101<!J
source, this return path may be provided directly to ground 100 1k!1
1000 100!J
or indirectly through a resistor to ground from pins 1 and/
or 3, as shown in Figure 3. If the return path is not pro-
vided, bias currents will cause the output to saturate. The Figure 2. Operating Connections for AD527
value of the resistor may be determined by dividing the
maximum allowable common mode voltage for the appli-
cation by the bias current of the instrumentation amplifier.
3. The resistors betWeen pins 10 and 13, (RSCALE) must equal
l00kn :t15% (Figure 2). If RSCALE is too low (below 85kn)
I For further details, refer to "An I.C. User's Guide to Decoupling,
the output swing of the AD521 is reduced. At values below
Grounding, and Making Things Go Right for a Change," by A. 'ceS
80kU and above 120kU the stability of the AD521 may be Paul Brokaw. This application note is available from Analog Devi
impaired. without charge upon request.

- - - . - - --- REV. A
-- -- j
- -- - -- - -
~

[ R. INPUT OFFSET AND OUTPUT OFFSET

AD521

When specifying offsets and other errors in an operational

amplifier, it is often convenient to refer these errors to the
inputs. This enables the user to calculate the maximum error
~ he would see at the output with any gain or circuit configura-
tion. An op amp with 1mV of input offset voltage, for
example, would produce 1V of offset at the output in a gain
of 1000 configuration.
":'

a). Transformer Coupled, Direct Return In the case of an instrumcntation amplifier, where the gain is
controlled in the amplifier, it is more convenient to separate
R.
errors into two categories. Those errors which simply add to
the output signal and are unaffected by the gain can be classi-
fied as output errors. Those which act as if they are associated
~ with the input signal, such that their effect at the output is
proportional to the gain, can be classified as input errors.

a
As an illustration, a typical ADS21 might have a +30mV output
offset and a -o.7mV input offset. In a unity gain configuration,
the total output offset would be +29.3mV or the sum of the ~

Not b). Thermocouple, Direct Return tWo. At a gain of 100, the output offset would be -40mV or:
30mV + 100(-o.7mV) =-40mV.
Reco
R.

By separating these errors, one can evaluate the total error

mme independent of the gain settings used, similar to the situation

with the input offset specifications on an op amp. In a given

nded gain configuration, both errors can be combined to give a total

error referred to the input (R.T.I.) or output (R.T.O.) by the

for n
following formula:
=input error + (output
ew D
Total Error R.T.I. error/gain)
c). AC Coupled, Indirect Return Total Error R.T.O. =(Gain x input error) + output error
Figure3. Ground Rerums for "Floating" Transducers esig
The offset trim adjustment (pins 4 and 6, Figure 2) is associ-
ated primarily with the output offset. At any gain it can be
used to introduce an output offset equal and opposite to the
input offset voltage multiplied by the gain. As a result, the
ns
total output offset can be reduced to zero.
As shown in Figure 6, the gain range on the ADS 21 can be
7
extended considerably by adding an attenuator in the sense
VOUT terminal feedback path (as well as adjusting the ratio, Rs/~).
Since the sense terminal is the inverting input to the output
amplifier, the additional gain to the output is controlled by
Rl and Rz. This gain factor is 1 + Rz/Rl'
1. ~~~~~:~~:~CK UPGAINLOSTBYR
2. INPUT SIGNAL MUST BE REDUCED IN RI
PROPORTION TO POWER SUPPLY VOLTAGE LEVEL

Figure 4. Operating Conditions for V/~VS= 10V V,

V+
VOUT

V2 R2
+ GAIN. ~
Villi RO
R,

OUTPUT COMMON

VOUT . [VREF +(~)(VI - V2)][R' ;,R2]

V-
Figure6. Circuit for utilizing some of the unique features of the
1
AD521. Note that gain changesintroduced by changing R1 and
Cx = 10fJ1rftwhen ft is the desired bandwidth. R2 will have a minimum effect on output offsst if the offsst is
(ft in kHz, Cx in J.l.F) carefully nulled at the highest gain setting.
Figure 5. Optional Compensation Circuit

R~lL--l1 INSTRUMENTA nON AMPLIFIERS 4-21

 AD521
RS
Where offset errors are critical, a resistor equal to the parallel
combination of Rl and Rz should be placed between pin 11
and VREF. This minimizes the offset errors resulting from the
input current flowing in Rl and Rz at the sense tenninal. Note VIN RG
that gain changes introduced by changing the Rl/Rz attenua- VOUT= VIN~
RG
tor will have a minimum effect on output offset if the offset
is carefully nulled at the highest gain setting. I
I VCM
When a predetennined output offset is desired, VREF can be - -.4'}---------
placed in series with pin 11. This offset is then multiplied by
L '-
the gain factor 1 + R2/Rl as shown in the equation of
Figure 6. Figure 7. Ground loop elimination. The reference input, Pin 11,
allows remote referencing of ground potential. Differences in
ground potentials are attenuated by the high CMRR of the
AD521.

+15V
I lOOk
3Oon

1 HFlOOk
Not 8 IOk
1 CHART
O.,&,.FT I RECORDER
14

Reco
mme
lOOk

---tt-
nded
F
2.5j.F

- =1 for n I 10Mn

-15V
O.I&,.F I I
3Oon

ew D
esig COMMON

Figure 8. Test circuit for measuring peak to peak noise in the

bandwidth 0.1Hz to 10Hz. Typical measurements are found by
reading the maximum peak to peak voltage noise of the device
ns
under test fD.U. T.) for 3 observation periods of 10 seconds each.

- - --- REV.A ~
- - - --- --- -