Single-Supply, Low Cost

Instrumentation Amplifier
AD8223
FEATURES CONNECTION DIAGRAM
Gain set with 1 resistor
–RG 1 8 +RG
Gain = 5 to 1000
–IN 2 – 7 +VS
Inputs
+IN 3 + 6 OUT
Voltage range to 150 mV below negative rail

06925-001
–VS 4 5 REF
25 nA maximum input bias current AD8223
30 nV/√Hz, RTI noise @ 1 kHz
Figure 1. 8-Lead SOIC (R) and 8-Lead MSOP (RM) Packages
Power supplies
Dual supply: ±2 V to ±12 V Table 1. Instrumentation Amplifiers by Category
Single supply: 3 V to 24 V General- Mil Low High Voltage
500 μA maximum supply current Purpose Zero Drift Grade Power PGA
AD82201 AD82311 AD620 AD6271 AD8250
APPLICATIONS AD8221 AD85531 AD621 AD6231 AD8251
Low power medical instrumentation AD8222 AD85551 AD524 AD8223 AD8253
Transducer interface AD82241 AD85561 AD526
Thermocouple amplifiers AD8228 AD85571 AD624
Industrial process controls 1
Rail-to-rail output.
Difference amplifiers
Low power data acquisition

GENERAL DESCRIPTION
The AD8223 is an integrated single-supply instrumentation to operate from a single supply, the AD8223 still provides
amplifier that delivers rail-to-rail output swing on a single excellent performance when operated from a dual voltage
supply (3 V to 24 V). The AD8223 conforms to the 8-lead supply (±2 V to ±12 V).
industry standard pinout configuration. Low power consumption (1.5 mW at 3 V), wide supply voltage
The AD8223 is simple to use: one resistor sets the gain. With no range, and rail-to-rail output swing make the AD8223 ideal for
external resistor, the AD8223 is configured for G = 5. With an battery-powered applications. The rail-to-rail output stage
external resistor, the AD8223 can be programmed for gains up maximizes the dynamic range when operating from low supply
to 1000. voltages. The AD8223 replaces discrete instrumentation
amplifier designs and offers superior linearity, temperature
The AD8223 has a wide input common-mode range and can
stability, and reliability in a minimum of space.
amplify signals that have a 150 mV common-mode voltage
below ground. Although the design of the AD8223 is optimized

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
AD8223

TABLE OF CONTENTS
Features .............................................................................................. 1  Gain Selection ............................................................................. 14 
Applications ....................................................................................... 1  Input Voltage Range ................................................................... 14 
Connection Diagram ....................................................................... 1  Reference Terminal .................................................................... 15 
General Description ......................................................................... 1  Input Protection ......................................................................... 15 
Revision History ............................................................................... 2  RF Interference (RFI)................................................................. 15 
Specifications..................................................................................... 3  Ground Returns for Input Bias Currents ................................ 16 
Single Supply ................................................................................. 3  Applications Information .............................................................. 17 
Dual Supply ................................................................................... 5  Basic Connection ....................................................................... 17 
Absolute Maximum Ratings............................................................ 7  Differential Output .................................................................... 17 
Thermal Resistance ...................................................................... 7  Output Buffering ........................................................................ 17 
ESD Caution .................................................................................. 7  Cables ........................................................................................... 17 
Pin Configuration and Function Descriptions ............................. 8  A Single-Supply Data Acquisition System .............................. 18 
Typical Performance Characteristics ............................................. 9  Amplifying Signals with Low Common-Mode Voltage ........ 18 
Theory of Operation ...................................................................... 14  Outline Dimensions ....................................................................... 19 
Amplifier Architecture .............................................................. 14  Ordering Guide .......................................................................... 20 

REVISION HISTORY
10/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 20
 AD8223

SPECIFICATIONS
SINGLE SUPPLY
TA = 25°C, −VS = 0 V, +VS = +5 V, and RL = 10 kΩ to 2.5 V, unless otherwise noted.

Table 2
AD8223A AD8223B
Parameter Conditions Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO
DC to 60 Hz with 1 kΩ Source VCM = 0 V to 3 V
Imbalance
G=5 80 86 dB
G = 10 86 90 dB
G = 100 90 96 dB
G = 1000 90 96 dB
NOISE VIN+ = VIN− = VREF = 0 V
Voltage Noise, 1 kHz
G=5 50 50 nV/√Hz
G = 1000 30 30 nV/√Hz
RTI, 0.1 Hz to 10 Hz
G=5 1.0 1.0 μV p-p
G = 1000 0.6 0.6 μV p-p
Current Noise, 1 kHz 70 70 fA/√Hz
0.1 Hz to 10 Hz 1.2 1.2 pA p-p
VOLTAGE OFFSET Total RTI error =
VOSI + VOSO/G
Input Offset, VOSI 250 100 μV
Over Temperature TA = −40°C to +85°C 400 160 μV
Average TC TA = −40°C to +85°C 2 1 μV/°C
Output Offset, VOSO 1500 1000 μV
Over Temperature TA = −40°C to +85°C 2000 1500 μV
Average TC TA = −40°C to +85°C 15 10 μV/°C
Offset Referred to Input vs. +VS = 4 V to 24 V,
Supply (PSR) −VS = 0 V
G=5 80 86 dB
G = 10 86 90 dB
G = 100 90 96 dB
G = 1000 90 96 dB
INPUT CURRENT
Input Bias Current 5 12 25 5 12 25 nA
Over Temperature TA = −40°C to +85°C 5 28 5 28 nA
Average Temperature TA = −40°C to +85°C 50 50 pA/°C
Coefficient
Input Offset Current 0.25 2 0.25 2 nA
Over Temperature TA = −40°C to +85°C 2.5 2.5 nA
Average Temperature TA = −40°C to +85°C 5 5 pA/°C
Coefficient
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G=5 125 125 kHz
G = 10 125 125 kHz
G = 100 50 50 kHz
G = 1000 5 5 kHz
Slew Rate 0.2 0.2 V/μs

Rev. 0 | Page 3 of 20
AD8223
AD8223A AD8223B
Parameter Conditions Min Typ Max Min Typ Max Unit
Settling Time to 0.01% Step size = 3.5 V
G=5 18 18 μs
G = 10 18 18 μs
G = 100 18 18 μs
G = 1000 85 85 μs
GAIN G = 5 + (80 kΩ/RG)
Gain Range 5 1000 5 1000 V/V
Gain Error1 VOUT = 0.05 V to 4.5 V
G=5 0.07 0.02 %
G = 10 0.10 0.3 0.10 0.2 %
G = 100 0.10 0.3 0.10 0.3 %
G = 1000 0.10 0.3 0.10 0.3 %
Nonlinearity VOUT = 0.05 V to 4.5 V
G=5 12 12 ppm
G = 1000 200 200 ppm
Gain vs. Temperature TA = −40°C to +85°C
G=5 10 2 ppm/°C
G > 51 50 50 ppm/°C
INPUT
Input Impedance
Differential 2||2 2||2 GΩ||pF
Common-Mode 2||2 2||2 GΩ||pF
Common-Mode Input Voltage VIN+ = VIN− (−VS) − (+VS) − (−VS) − (+VS) − V
Range2 0.15 1.5 0.15 1.5
OUTPUT
Output Swing RL = 10 kΩ to ground +0.01 (+VS) − +0.01 (+VS) − V
0.5 0.5
RL = 100 kΩ to ground +0.01 (+VS) − +0.01 (+VS) − V
0.15 0.15
REFERENCE INPUT
RIN 60 ±20% 60 ±20% kΩ
IIN VIN+ = VIN− = VREF = 0 V +10 +20 +10 +20 μA
Voltage Range −VS +VS −VS +VS V
Gain to Output 1± 1± V
0.0002 0.0002
POWER SUPPLY
Operating Range +3 +24 +3 +24 V
Quiescent Current 350 500 350 500 μA
Over Temperature TA = −40°C to +85°C 600 600 μA
TEMPERATURE RANGE
For Specified Performance -40 +85 −40 +85 °C
1
Does not include effects of external resistor, RG.
2
Total input range depends on common-mode voltage, differential voltage, and gain. See Figure 18 through Figure 21, and the Input Voltage Range section in the
Theory of Operation section for more information.

Rev. 0 | Page 4 of 20
 AD8223
DUAL SUPPLY
TA = 25°C, −VS = −12 V, +VS = +12 V, and RL = 10 kΩ to ground, unless otherwise noted.1

Table 3.
AD8223A AD8223B
Parameter Conditions Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO
DC to 60 Hz with 1 kΩ Source VCM = −10 V to 10 V
Imbalance
G=5 80 86 dB
G = 10 86 90 dB
G = 100 90 96 dB
G = 1000 90 96 dB
NOISE VIN+ = VIN− = VREF = 0 V
Voltage Noise, 1 kHz
G=5 50 50 nV/√Hz
G = 1000 30 30 nV/√Hz
RTI, 0.1 Hz to 10 Hz
G=5 1.0 1.0 μV p-p
G = 1000 0.6 0.6 μV p-p
Current Noise, 1 kHz 70 70 fA/√Hz
0.1 Hz to 10 Hz 1.2 1.2 pA p-p
VOLTAGE OFFSET Total RTI error =
VOSI + VOSO/G
Input Offset, VOSI 250 100 μV
Over Temperature TA = −40°C to +85°C 400 160 μV
Average TC TA = −40°C to +85°C 2 1 μV/°C
Output Offset, VOSO 1500 1000 μV
Over Temperature TA = −40°C to +85°C 2000 1500 μV
Average TC TA = −40°C to +85°C 15 10 μV/°C
Offset Referred to Input vs. +VS = 5 V to 12 V,
Supply (PSR) −VS = −5 V to −12 V
G=5 80 86 dB
G = 10 86 90 dB
G = 100 90 96 dB
G = 1000 90 96 dB
INPUT CURRENT
Input Bias Current 5 12 25 5 12 25 nA
Over Temperature TA = −40°C to +85°C 5 28 5 28 nA
Average Temperature TA = −40°C to +85°C 50 50 pA/°C
Coefficient
Input Offset Current 0.25 2 0.25 2 nA
Over Temperature TA = −40°C to +85°C 2.5 2.5 nA
Average Temperature TA = −40°C to +85°C 5 5 pA/°C
Coefficient
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G=5 200 200 kHz
G = 10 200 200 kHz
G = 100 70 70 kHz
G = 1000 7 7 kHz
Slew Rate 0.3 0.3 V/μs
Settling Time to 0.01% Step size = 10 V
G=5 30 30 μs
G = 10 30 30 μs
G = 100 30 30 μs
G = 1000 150 150 μs

Rev. 0 | Page 5 of 20
AD8223
AD8223A AD8223B
Parameter Conditions Min Typ Max Min Typ Max Unit
GAIN G = 5 + (80 kΩ/RG)
Gain Range 5 1000 5 1000 V/V
Gain Error2 VOUT = −10 V to +10 V
G=5 0.07 0.02 %
G = 10 0.10 0.3 0.10 0.2 %
G = 100 0.10 0.3 0.10 0.3 %
G = 1000 0.10 0.3 0.10 0.3 %
Nonlinearity VOUT = −10 V to +10 V
G=5 5 5 ppm
G = 1000 30 30 ppm
Gain vs. Temperature TA = −40°C to +85°C
G=5 10 2 ppm/°C
G > 51 50 50 ppm/°C
INPUT
Input Impedance
Differential 2||2 2||2 GΩ||pF
Common-Mode 2||2 2||2 GΩ||pF
Common-Mode Input Voltage VIN+ = VIN− (−VS) − (+VS) − (−VS) − (+VS) − V
Range3 0.15 1.5 0.15 1.5
OUTPUT
Output Swing RL = 10 kΩ to ground (−VS) + (+VS) − (−VS) + (+VS) − V
0.3 0.8 0.3 0.8
RL = 100 kΩ to ground (−VS) + (+VS) − (−VS) + (+VS) − V
0.1 0.3 0.1 0.3
REFERENCE INPUT
RIN 60 ±20% 60 ±20% kΩ
IIN VIN+ = VIN− = VREF = 0 V +10 +20 +10 +20 μA
Voltage Range −VS +VS −VS +VS V
Gain to Output 1± 1± V
0.0002 0.0002
POWER SUPPLY
Operating Range ±2 ±12 ±2 ±12 V
Quiescent Current 650 650 μA
Over Temperature TA = −40°C to +85°C 850 850 μA
TEMPERATURE RANGE
For Specified Performance −40 +85 −40 +85 °C
1
Because maximum supply voltage is 24 V between the negative and positive supply, these specifications at ±12V are at the part’s limit. Operation at a nominal supply
voltage slightly less than ±12 V is recommended to allow for power supply tolerances.
2
Does not include effects of external resistor, RG.
3
Total input range depends on common-mode voltage, differential voltage, and gain. See Figure 18 through Figure 21 and the Input Voltage Range section in the
Theory of Operation section for more information.

Rev. 0 | Page 6 of 20
 AD8223

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE
Table 4.
Parameter Rating θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Supply Voltage ±12 V
Internal Power Dissipation 650 mW Specification is for the device in free air.
Differential Input Voltage ±VS
Table 5. Thermal Resistance
Output Short-Circuit Duration Indefinite
Storage Temperature Range (R, RM) −65°C to +125°C Package Type θJA Unit
Operating Temperature Range −40°C to +85°C 8-Lead SOIC (R) 155 °C/W
Lead Temperature (Soldering, 10 sec) 300°C 8-Lead MSOP (RM) 200 °C/W
ESD (Human Body Model) 1.5 kV
ESD (Charge Device Model) 500 V
ESD CAUTION
ESD (Machine Model) 100 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. 0 | Page 7 of 20
AD8223

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

–RG 1 8 +RG

–IN 2 AD8223 7 +VS

TOP VIEW
+IN 3 (Not to Scale) 6 OUT

06925-002
–VS 4 5 REF

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Descriptions
1 −RG Gain Resistor Terminal.
2 −IN Negative Input.
3 +IN Positive Input.
4 −VS Negative Supply.
5 REF Reference. Connect to a low impedance source. Output is referenced to this node.
6 OUT Output.
7 +VS Positive Supply.
8 +RG Gain Resistor Terminal.

Rev. 0 | Page 8 of 20
 AD8223

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = ±5 V, RL = 10 kΩ, unless otherwise noted.
1000
N = 4720
MEAN = –12.9448
700 SD = 0.317868

VOLTAGE NOISE DENSITY (nV/ Hz)

600
NUMBER OF UNITS

500

400
100
G=5
G = 10
300

200

100

06925-061
G = 1000

06925-050
BW LIMIT G = 100
0 BW LIMIT
10
–13.8 –13.5 –13.2 –12.9 –12.6 –12.3 –12.0 0.1 1 10 100 1k 10k 100k
INPUT BIAS CURRENT (nA) FREQUENCY (Hz)

Figure 3. Typical Distribution of Input Bias Current Figure 6. Voltage Noise Density vs. Frequency

25
N = 4720
MEAN = –0.00571517
1000 SD = 0.172282
20

800
NUMBER OF UNITS

15
IBIAS (nA)

600

10
400

200 5
06925-062

06925-064
0
0
–0.9 –0.6 –0.3 0 0.3 0.6 0.9 1.2 –60 –40 –20 0 20 40 60 80 100 120 140
INPUT OFFSET CURRENT (nA) TEMPERATURE (°C)
Figure 4. Typical Distribution of Input Offset Current Figure 7. IBIAS vs. Temperature

N = 5036 1000
1400 MEAN = –0.00336179
SD = 0.00155048
CURRENT NOISE DENSITY (fA/ Hz)

1200
NUMBER OF UNITS

1000

800
100
600

400

200
06925-063

06925-065

0
10
–0.015 –0.010 –0.005 0 0.005 0.010 0.015 0.1 1 10 100
0.01 1k
GAIN ERROR, G = 5 (%)
FREQUENCY (Hz)
Figure 5. Typical Distribution for Gain Error (G = 5) Figure 8. Current Noise Density vs. Frequency

Rev. 0 | Page 9 of 20
AD8223
18 120
G = 1000
16 110
±VS = ±5V ±VS = ±2.5V
14 100
±VS = ±12V G=5
G = 100 G = 10
12 90

CMRR (dB)
IBIAS (nA)

10 80

8 70

6 60

4 50

40

06925-055
2

06925-013
0 30
–12 –10 –8 –6 –4 –2 0 2 4 6 8 10 1 10 100 1k 10k 100k
CMV (V) FREQUENCY (Hz)

Figure 9. IBIAS vs. CMV Figure 12. CMRR vs. Frequency, ±VS = ±12

120
G = 1000
110

100
G=5
90 G = 100 G = 10
CMRR (dB)

80

70

60

50

40

06925-056
06925-066

500fA/DIV 1s/DIV
30
1 10 100 1k 10k 100k
FREQUENCY (Hz)

Figure 10. 0.1 Hz to 10 Hz Current Noise Figure 13. CMRR vs. Frequency, +VS = +5 V
70
G = 1000
60
G = 1000
50
G = 100
40

30
GAIN (dB)

G = 10
20

10 G=5
G=5
0

–10
06925-018

–20
06925-054

0.5µV/DIV 1s/DIV
–30
100 1k 10k 100k 1M
FREQUENCY (Hz)

Figure 11. 0.1 Hz to 10 Hz RTI and RTO Voltage Noise Figure 14. Gain vs. Frequency, ±VS = ±12 V

Rev. 0 | Page 10 of 20
 AD8223
70 4
G = 1000
60 3 ±VS = ±5V

50 2

COMMON-MODE INPUT (V)

G = 100
40 1
±VS = ±2.5V
30 0
GAIN (dB)

G = 10 +VS = +5V
20 –1

10 G=5 –2

0 –3

–10 –4

06925-070
06925-067
–20 –5

–30 –6
100 1k 10k 100k 1M –6 –4 –2 0 2 4 6
FREQUENCY (Hz) MAXIMUM OUTPUT VOLTAGE (V)

Figure 15. Gain vs. Frequency, +VS = +5 V Figure 18. Common-Mode Input vs. Maximum Output Voltage,
G = 5, Small Supplies
25 15

±12V
10
20
OUTPUT VOLTAGE (V p-p)

COMMON-MODE INPUT (V)

5
15

0
±5V
10
–5

±2.5V
5
–10
06925-068

06925-071
0 –15
0.1 1 10 100 –15 –10 –5 0 5 10 15
FREQUENCY (kHz) MAXIMUM OUTPUT VOLTAGE (V)
Figure 16. Large Signal Frequency Response Figure 19. Common-Mode Input vs. Maximum Output Voltage,
G = 5, ±VS = ±12 V
0.04 4

0.38 3 ±VS = ±5V

0.36 2
COMMON-MODE INPUT (V)

0.34 1
SLEW RATE (V/μs)

±VS = ±2.5V
0.32 0
+VS = +5V
0.30 –1

0.28 –2

0.26 –3

0.24 –4
06925-069

06925-072

0.22 –5

0.20 –6
2 4 6 8 10 12 14 –6 –4 –2 0 2 4 6
SUPPLY VOLTAGE (±VS) MAXIMUM OUTPUT VOLTAGE (V)

Figure 17. Slew Rate vs. Supply Voltage Figure 20. Common-Mode Input vs. Maximum Output Voltage,
G = 100, Small Supplies

Rev. 0 | Page 11 of 20
AD8223
15 120
G = 1000

10 100
COMMON-MODE INPUT (V)

5 80
G = 100

PSRR (dB)
0 60

G = 10
–5 40 G=5

–10 20

06925-073

06925-025
–15 0
–15 –10 –5 0 5 10 15 1 10 100 1k 10k 100k
MAXIMUM OUTPUT VOLTAGE (V) FREQUENCY (Hz)

Figure 21. Common-Mode Input vs. Maximum Output Voltage, Figure 24. Negative PSRR vs. Frequency, ±VS = ±12 V
G = 100, ±VS = ±12 V

140

120
5V/DIV
G = 1000
100
G = 100
PSRR (dB)

80

G = 10
60
G=5
40 0.1%/DIV

20
06925-023

06925-051
100µs/DIV
0
1 10 100 1k 10k 100k
FREQUENCY (Hz)

Figure 22. Positive PSRR vs. Frequency, ±VS = ±12 V Figure 25. Large Signal Response, G = 5

140

120
5V/DIV
G = 1000
100
G = 100
PSRR (dB)

80

G = 10
60

G=5
40 0.1%/DIV

20
06925-024

06925-052

100µs/DIV
0
1 10 100 1k 10k 100k
FREQUENCY (Hz)

Figure 23. Positive PSRR vs. Frequency, +VS = +5 V Figure 26. Large Signal Pulse Response, G = 100, CL = 100 pF

Rev. 0 | Page 12 of 20
 AD8223

5V/DIV

0.1%/DIV
2

06925-053

06925-034
100µs/DIV 20mV/DIV 100µs/DIV

Figure 27. Large Signal Pulse Response, G = 1000, CL = 100 pF Figure 29. Small Signal Pulse Response, G = 1000, RL = 25 kΩ, CL = 100 pF

+VS

REFERRED TO SUPPLY VOLTAGES

G=5

OUTPUT VOLTAGE SWING (V)

–1 SOURCING
G = 10
G = 100

–2

+2

+1 SINKING

06925-074
2

–VS
06925-028

0.01 0.1 1 10
20mV/DIV 10µs/DIV
OUTPUT CURRENT (mA)

Figure 28. Small Signal Pulse Response, G = 5, 10, 100; RL = 10 kΩ Figure 30. Output Voltage Swing vs. Output Current

Rev. 0 | Page 13 of 20
AD8223

THEORY OF OPERATION
AMPLIFIER ARCHITECTURE GAIN SELECTION
The AD8223 is an instrumentation amplifier based on a Placing a resistor across the RG terminals sets the gain of the
classic 3-op amp approach, modified to ensure operation AD8223, which can be calculated by referring to Table 7 or by
even at common-mode voltages at the negative supply rail. using the following gain equation:
The architecture allows lower voltage offsets, better CMRR,
80 kΩ
and higher gain accuracy than competing instrumentation RG 
amplifiers in its class. G5
POSITIVE SUPPLY
7 Table 7. Gains Achieved Using 1% Resistors
1% Standard Table
+
INVERTING Value of RG (Ω) Desired Gain Calculated Gain
2 –
26.7 k 8 7.99
4 8kΩ 10kΩ 50kΩ
1 15.8 k 10 10.1
– OUT 5.36 k 20 19.9
GAIN
+ 6
2.26 k 40 40.4
8kΩ 10kΩ 50kΩ REF
8
7 5 1.78 k 50 49.9
– 845 100 99.7
NON- 412 200 199
INVERTING +
3
162 500 499
06925-038

4 80.6 1000 998

NEGATIVE SUPPLY

Figure 31. Simplified Schematic The AD8223 defaults to G = 5 when no gain resistor is used. Add
the tolerance and gain drift of the RG resistor to the specifications
Figure 31 shows a simplified schematic of the AD8223. The
of the AD8223 to determine the total gain accuracy of the system.
AD8223 has three stages. In the first stage, the input signal is
When the gain resistor is not used, gain depends only on
applied to PNP transistors. These PNP transistors act as voltage
internal resistor matching, so gain error and gain drift are
buffers and allow input voltages below ground. The second
minimal.
stage consists of a pair of 8 kΩ resistors, the RG resistor, and a
pair of amplifiers. This stage allows the amplification of the INPUT VOLTAGE RANGE
AD8223 to be set with a single external resistor. The third stage The 3-op amp architecture of the AD8223 applies gain and then
is a differential amplifier composed of an op amp, two 10 kΩ removes the common-mode voltage. Therefore, internal nodes
resistors, and two 50 kΩ resistors. This stage removes the in the AD8223 experience a combination of both the gained
common-mode signal and applies an additional gain of 5. signal and the common-mode signal. This combined signal can
The transfer function of the AD8223 is be limited by the voltage supplies even when the individual input
VOUT = G(VIN+ − VIN−) + VREF and output signals are not. To determine whether the signal can be
limited, refer to Figure 18 through Figure 21. Alternatively, use
where: the parameters in the Specifications section to verify that the input
80 kΩ and output are not limited and then use the following formula to
G5 make sure the internal nodes are not limited.
RG
To check if it is limited by the internal nodes,
VDIFF  Gain
 VS  0.01 V  0.6  VCM    VS  0.1 V
10
If more common-mode range is required, a solution is to apply less
gain in the instrumentation amplifier and more in a later stage.

Rev. 0 | Page 14 of 20
 AD8223
REFERENCE TERMINAL RF INTERFERENCE (RFI)
The output voltage of the AD8223 is developed with respect to RF rectification is often a problem when amplifiers are used in
the potential on the reference terminal. This is useful when the applications where there are strong RF signals. The disturbance
output signal needs to be offset to a precise midsupply level. For can appear as a small dc offset voltage. High frequency signals
example, a voltage source can be tied to the REF pin to level- can be filtered with a low-pass, R-C network placed at the input
shift the output so that the AD8223 can drive a single-supply of the instrumentation amplifier, as shown in Figure 34. The
ADC. The REF pin is protected with ESD diodes and should filter limits the input signal bandwidth according to the follow-
not exceed either +VS or −VS by more than 0.3 V. ing relationship:
For best performance, keep the source impedance to the REF 1
FilterFreqDiff 
terminal below 5 Ω. As shown in Figure 31, the reference 2 R(2CD  CC )
terminal, REF, is at one end of a 50 kΩ resistor. Additional
1
impedance at the REF terminal adds to this resistor and results FilterFreqCM 
2 RCC
in poorer CMRR performance.
INCORRECT CORRECT where CD ≥ 10CC.
+15V

+
0.1µF 10µF
AD8223 AD8223
CC
VREF
1nF
VREF R +IN
+
+ 4.02kΩ
CD R1 VOUT
OP2177 47nF 499Ω AD8223
– R
06925-039

REF
–
4.02kΩ –IN
CC
Figure 32. Driving the Reference Pin 1nF

0.1µF 10µF +
INPUT PROTECTION

06925-041
Internal supply referenced clamping diodes allow the input, –15V

reference, output, and gain terminals of the AD8223 to safely Figure 34. RFI Suppression
withstand overvoltages of 0.3 V above or below the supplies. Figure 34 shows an example in which the differential filter fre-
This is true for all gains, and for power-on and power-off. This quency is approximately 400 Hz, and the common-mode filter
last case is particularly important because the signal source and frequency is approximately 40 kHz. The typical dc offset shift
amplifier can be powered separately. over frequency is less than 1.5 μV, and the RF signal rejection
If the overvoltage is expected to exceed this value, limit the of the circuit is better than 71 dB.
current through these diodes to about 10 mA using external The resistors were selected to be large enough to isolate the
current limiting resistors. This is shown in Figure 33. The size circuit input from the capacitors but not large enough to
of this resistor is defined by the supply voltage and the required significantly increase the circuit noise. Choose values of R and
overvoltage protection. CC to minimize RFI. Mismatch between the R × CC at positive
+VS input and the R × CC at negative input degrades the CMRR of
1 = 10mA MAX the AD8223. Because of their higher accuracy and stability,
RLIM
+
VOVER COG/NPO type ceramic capacitors are recommended for the
RG
CC capacitors. The dielectric for the CD capacitor is not as
AD8223 OUT
RLIM critical.
VOVER – VOVER – VS + 0.7V
RLIM =
10mA
06925-040

–VS

Figure 33. Input Protection

Rev. 0 | Page 15 of 20
AD8223
INCORRECT CORRECT
GROUND RETURNS FOR INPUT BIAS CURRENTS
+VS +VS
Input bias currents are those dc currents that must flow to bias
the input transistors of an amplifier. These are usually transistor
base currents. When amplifying floating input sources such as
transformers or ac-coupled sources, there must be a direct dc AD8223 AD8223
path into each input so that the bias current can flow. Figure 35 REF REF

shows how a bias current path can be provided for the cases of
transformer coupling, capacitive ac-coupling, and a thermo-
–VS –VS
couple application.
TRANSFORMER TRANSFORMER
In dc-coupled resistive bridge applications, providing this path
is generally not necessary because the bias current simply flows +VS +VS
from the bridge supply through the bridge and into the amplifier.
However, if the impedances that the two inputs see are large and
differ by a large amount (>10 kΩ), the offset current of the input
AD8223 AD8223
stage causes dc errors proportional to the input offset voltage of
REF REF
the amplifier.
10MΩ

–VS –VS

THERMOCOUPLE THERMOCOUPLE

+VS +VS

C C

1 R
fHIGH-PASS = 2πRC
AD8223 AD8223
C C
REF REF

–VS –VS

06925-042
CAPACITIVELY COUPLED CAPACITIVELY COUPLED

Figure 35. Creating an IBIAS Path

Rev. 0 | Page 16 of 20
 AD8223

APPLICATIONS INFORMATION
+VS +VS
+2V TO +12V +3V TO +24V

+ +
0.1µF 10µF 0.1µF 10µF

+ +
RG RG
VIN RG OUTPUT VOUT VIN RG OUTPUT VOUT
RG REF RG REF
– –
REF (INPUT) REF (INPUT)

0.1µF 10µF
+

–2V TO –12V
–VS

06925-043
A. DUAL SUPPLY B. SINGLE SUPPLY
Figure 36. Basic Connections

BASIC CONNECTION OUTPUT BUFFERING

Figure 36 shows the basic connection circuit for the AD8223. The AD8223 is designed to drive loads of 10 kΩ or greater. If
The +VS and −VS terminals are connected to the power supply. the load is less than this value, buffer the AD8223 output with a
The supply can be either bipolar (VS = ±2 V to ±12 V) or single precision single-supply op amp such as the OP113. This op amp
supply (−VS = 0 V, +VS = +3 V to +24 V). Power supplies should can swing from 0 V to 4 V on its output while driving a load as
be capacitively decoupled close to the power pins of the device. small as 600 Ω.
For best results, use surface-mount 0.1 μF ceramic chip capacitors 5V
and 10 μF electrolytic tantalum capacitors. 0.1µF 5V
The input voltage, which can be either single-ended (tie either 0.1µF
−IN or +IN to ground) or differential, is amplified by the +
VIN RG AD8223 +
programmed gain. The output signal appears as the voltage –
REF OP113 VOUT
difference between the output pin and the externally applied –

06925-045
voltage on the REF input.
DIFFERENTIAL OUTPUT Figure 38. Output Buffering
Figure 37 shows how to create a differential output in-amp. An
CABLES
OP1177 op amp creates the inverted output. Because the op
amp drives the AD8223 reference pin, the AD8223 can still Receiving from a Cable
ensure that the differential voltage is correct. Errors from the In many applications, shielded cables are used to minimize
op amp or mismatched resistors are common to both outputs noise; for best CMR over frequency, the shield should be
and are thus common mode. These common-mode errors properly driven. Figure 39 shows an active guard drive that
should be rejected by the next device in the signal chain. is configured to improve ac common-mode rejection by
bootstrapping the capacitances of input cable shields, thus
+IN minimizing the capacitance mismatch between the inputs.
AD8223 +OUT +VS
–INPUT
–IN 2
1 7
REF 20kΩ VREF RG
100Ω 2
AD8031
RG
AD8223 6 VOUT
– + 2 5
8
20kΩ OP1177 4 REFERENCE
3
06925-046

+INPUT
–VS
06925-044

Figure 39. Common-Mode Shield Driver

–OUT

Figure 37. Differential Output Using Op Amp

Rev. 0 | Page 17 of 20
AD8223
Driving a Cable The bridge circuit is excited by a +5 V supply. The full-scale output
All cables have a certain capacitance per unit length, which voltage from the bridge (±10 mV), therefore, has a common-
varies widely with cable type. The capacitive load from the mode level of 2.5 V. The AD8223 removes the common-mode
cable may cause peaking in the output response of the AD8223. component and amplifies the input signal by a factor of 100
To reduce the peaking, use a resistor between the AD8223 and (RG = 1.02 kΩ). This results in an output signal of ±1 V. To
the cable. Because cable capacitance and desired output response prevent this signal from running into the AD8223 ground rail, the
vary widely, this resistor is best determined empirically. A good voltage on the REF pin must be raised to at least 1 V. In this
starting point is 75 Ω. example, the 2 V reference voltage from the AD7776 ADC is
used to bias the AD8223 output voltage to 2 V ± 1 V, which
The AD8232 operates at a low enough frequency that transmission
corresponds to the input range of the ADC.
line effects are rarely an issue; therefore, the resistor need not
match the characteristic impedance of the cable. AMPLIFYING SIGNALS WITH LOW COMMON-
MODE VOLTAGE
Because the common-mode input range of the AD8223 extends
AD8223 0.15 V below ground, it is possible to measure small differential
(DIFF OUT)
signals that have low, or no, common-mode components. Figure 42
shows a thermocouple application in which one side of the J-type
thermocouple is grounded.
5V

0.1µF
AD8223
(SINGLE OUT)
+
J-TYPE RG
AD8223 VOUT
06925-047

THERMOCOUPLE 1.02kΩ
– REF
2V
Figure 40. Driving a Cable

06925-049
Figure 42. Amplifying Bipolar Signals with Low Common-Mode Voltage
A SINGLE-SUPPLY DATA ACQUISITION SYSTEM
Over a temperature range of −200°C to +200°C, the J-type
Interfacing bipolar signals to single-supply analog-to-digital thermocouple delivers a voltage ranging from −7.890 mV
converters (ADCs) presents a challenge. The bipolar signal to +10.777 mV. A programmed gain on the AD8223 of 100
must be mapped into the input range of the ADC. Figure 41 (RG = 845) and a voltage on the AD8223 REF pin of 2 V results
shows how this translation can be achieved. in the AD8223 output voltage ranging from 1.110 V to 3.077 V
5V
5V 5V
relative to ground.
0.1µF
0.1µF

AD7776
+
RG
±10mV AD8223 AIN
1.02kΩ
–
REF
REFOUT
REFIN
06925-048

Figure 41. A Single-Supply Data Acquisition System

Rev. 0 | Page 18 of 20
 AD8223

OUTLINE DIMENSIONS
3.20
3.00
2.80

8 5 5.15
3.20
4.90
3.00
4.65
2.80 1
4

PIN 1
0.65 BSC
0.95
0.85 1.10 MAX
0.75
0.80
0.15 0.38 8° 0.60
0.23
0.00 0.22 0° 0.40
0.08
COPLANARITY SEATING
0.10 PLANE

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 43. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)
Dimensions shown in millimeters

5.00 (0.1968)
4.80 (0.1890)

8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4

1.27 (0.0500) 0.50 (0.0196)

BSC 45°
1.75 (0.0688) 0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532)
8°
0.10 (0.0040) 0°
COPLANARITY 0.51 (0.0201)
0.10 1.27 (0.0500)
0.31 (0.0122) 0.25 (0.0098)
SEATING 0.40 (0.0157)
PLANE 0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-A A

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
012407-A

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 44. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)

Rev. 0 | Page 19 of 20
AD8223
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8223AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8223AR-RL −40°C to +85°C 8-Lead SOIC_N,13" Tape and Reel R-8
AD8223AR-R7 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8223ARM −40°C to +85°C 8-Lead MSOP RM-8 Y0U
AD8223ARM-RL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y0U
AD8223ARM-R7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y0U
AD8223ARMZ1 −40°C to +85°C 8-Lead MSOP RM-8 Y0Q
AD8223ARMZ-RL1 −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y0Q
AD8223ARMZ-R71 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y0Q
AD8223ARZ1 −40°C to +85°C 8-Lead SOIC_N R-8
AD8223ARZ-RL1 −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8223ARZ-R71 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8223BR −40°C to +85°C 8-Lead SOIC_N R-8
AD8223BR-RL −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8223BR-R7 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8223BRM −40°C to +85°C 8-Lead MSOP RM-8 Y0V
AD8223BRM-RL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y0V
AD8223BRM-R7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y0V
AD8223BRMZ1 −40°C to +85°C 8-Lead MSOP RM-8 Y0R
AD8223BRMZ-RL1 −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y0R
AD8223BRMZ-R71 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y0R
AD8223BRZ1 −40°C to +85°C 8-Lead SOIC_N R-8
AD8223BRZ-RL1 −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8223BRZ-R71 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8
1
Z = RoHS Compliant Part.

©2008 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D06925-0-10/08(0)

Rev. 0 | Page 20 of 20