STW26NM60

N-CHANNEL 600V - 0.125Ω - 30A TO-247

MDmesh™ MOSFET

Table 1: General Features Figure 1: Package

TYPE VDSS RDS(on) ID

STW26NM60 600 V < 0.135 Ω 30 A

■ TYPICAL RDS(on) = 0.125 Ω
■ HIGH dv/dt AND AVALANCHE CAPABILITIES
■ IMPROVED ESD CAPABILITY
■ LOW INPUT CAPACITANCE AND GATE
CHARGE
■ LOW GATE INPUT RESISTANCE
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3
2

DESCRIPTION TO-247
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1

The MDmesh™ is a new revolutionary MOSFET

od
technology that associates the Multiple Drain pro-
cess with the Company’s PowerMESH™ horizon-
P r
tal layout. The resulting product has an
outstanding low on-resistance, impressively high
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Figure 2: Internal Schematic Diagram
dv/dt and excellent avalanche characteristics. The
adoption of the Company’s proprietary strip tech-
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nique yields overall dynamic performance that is
significantly better than that of similar competi-
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tion’s products.

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APPLICATIONS
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The MDmesh™ family is very suitable for increas-
ing power density of high voltage converters allow-

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ing system miniaturization and higher efficiencies.
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Table 2: Order Codes

b s SALES TYPE MARKING PACKAGE PACKAGING

O STW26NM60 W26NM60 TO-247 TUBE

Rev. 5
February 2005 1/9
 STW26NM60

Table 3: Absolute Maximum ratings

Symbol Parameter Value Unit
VDS Drain-source Voltage (VGS = 0) 600 V
VDGR Drain-gate Voltage (RGS = 20 kΩ) 600 V
VGS Gate- source Voltage ± 30 V
ID Drain Current (continuous) at TC = 25°C 30 A
ID Drain Current (continuous) at TC = 100°C 18.9 A
IDM (
) Drain Current (pulsed) 120 A
PTOT Total Dissipation at TC = 25°C 313 W
Derating Factor 2.5 W/°C
VESD(G-S) Gate source ESD(HBM-C=100pF, R=1.5KΩ) 6000 V
dv/dt (1) Peak Diode Recovery voltage slope 15 V/ns
Tj Operating Junction Temperature
-55 to 150 °C
Tstg Storage Temperature
(
) Pulse width limited by safe operating area
s)
t(
(1) ISD ≤26A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ T JMAX.

Table 4: Thermal Data

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Rthj-case Thermal Resistance Junction-case Max 0.4
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Rthj-amb
Tl
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering Purpose P r
62.5
300
°C/W
°C

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Table 5: Avalanche Characteristics
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Symbol
IAR
Parameter
Avalanche Current, Repetitive or Not-Repetitive
b s Max Value
13
Unit
A
(pulse width limited by Tj max)

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EAS Single Pulse Avalanche Energy

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(starting Tj = 25 °C, ID = IAR, VDD = 50 V)

(
740 mJ

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ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)

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Table 6: Gate-Source Zener Diode
P
Symbol
BVGSO
et e Parameter
Gate-Source Breakdown
Test Conditions
Igss=± 1mA (Open Drain)
Min.
30
Typ. Max. Unit
V

o l Voltage

b s
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
OESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.

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 STW26NM60

Table 7: On /Off
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source Breakdown ID = 250 µA, VGS = 0 600 V
Voltage
IDSS Zero Gate Voltage VDS = Max Rating 10 µA
Drain Current (VGS = 0) VDS = Max Rating, TC = 125°C 100 µA
IGSS Gate-body Leakage VGS = ± 20 V ± 10 µA
Current (VDS = 0)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 3 4 5 V
RDS(on Static Drain-source On VGS = 10 V, ID = 13 A 0.125 0.135 Ω
Resistance

Table 8: Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit
gfs (1) Forward Transconductance VDS = 15 V , ID = 13 A 20 S
Ciss Input Capacitance VDS = 25 V, f = 1 MHz, 2900

s) pF

t(
Coss Output Capacitance VGS = 0 900 pF
Crss Reverse Transfer 40 pF
Capacitance

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COSS eq (3). Equivalent Output
Capacitance
VGS = 0 V, VDS = 0 to 400 V

o
300
d pF

td(on)
tr
Turn-on Delay Time
Rise Time
VDD = 300 V, ID = 13 A,
RG = 4.7 Ω, VGS = 10 V P r 35
22
ns
ns
td(off) Turn-off-Delay Time (see Figure 15)
te 14 ns

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tf Fall Time 20 ns

so
Qg Total Gate Charge VDD = 480 V, ID = 26 A, 73 102 nC
Qgs Gate-Source Charge VGS = 10 V 20 nC
Qgd Gate-Drain Charge
b
(see Figure 18)

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37 nC

Table 9: Source Drain Diode

) -
Symbol Parameter
( s Test Conditions Min. Typ. Max. Unit
ISD
ISDM (2)
Source-drain Current

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Source-drain Current (pulsed)
26
104
A
A
VSD (1)
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Forward On Voltage ISD = 26 A, VGS = 0 1.5 V
trr
Qrr
Pr
Reverse Recovery Time
Reverse Recovery Charge
ISD = 26 A, di/dt = 100 A/µs
VDD = 100V
450
7
ns
µC
IRRM

et e
Reverse Recovery Current (see Figure 16) 30.5 A
trr
Qrr
o l Reverse Recovery Time
Reverse Recovery Charge
ISD = 26 A, di/dt = 100 A/µs
VDD = 100V, Tj = 150°C
560
9
ns
µC

bs
IRRM Reverse Recovery Current (see Figure 16) 32.5 A
(1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.

O
(2) Pulse width limited by safe operating area.
(3) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.

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 STW26NM60

Figure 3: Safe Operating Area Figure 6: Thermal Impedance

Figure 4: Output Characteristics Figure 7: Transfer Characteristics

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Figure 5: Transconductance
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 STW26NM60

Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations

Figure 10: Normalized Gate Thereshold Volt-

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Figure 13: Normalized On Resistance vs Tem-
s
t(
age vs Temperature perature

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Figure 11: Dource-Drain Diode Forward Char-
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acteristics

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 STW26NM60

Figure 14: Unclamped Inductive Load Test Cir- Figure 17: Unclamped Inductive Wafeform
cuit

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Figure 15: Switching Times Test Circuit For
Resistive Load t(
Figure 18: Gate Charge Test Circuit

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Figure 16: Test Circuit For Inductive Load
Switching and Diode Recovery Times

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 STW26NM60

TO-247 MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 4.85 5.15 0.19 0.20
A1 2.20 2.60 0.086 0.102
b 1.0 1.40 0.039 0.055
b1 2.0 2.40 0.079 0.094
b2 3.0 3.40 0.118 0.134
c 0.40 0.80 0.015 0.03
D 19.85 20.15 0.781 0.793
E 15.45 15.75 0.608 0.620
e 5.45 0.214

s)
t(
L 14.20 14.80 0.560 0.582
L1
L2
3.70
18.50
4.30 0.14
0.728 c
0.17

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øP 3.55 3.65 0.140

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øR
S
4.50
5.50
5.50 0.177

P r
0.216
0.216

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 STW26NM60

Table 10: Revision History

Date Revision Description of Changes

24-June-2004 4 New Stylesheet. No Content Change
04-Feb-2004 5 New Id current on title in first page

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 STW26NM60

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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

l t
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

e
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

o
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

s
O b The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners

© 2005 STMicroelectronics - All Rights Reserved

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