STP5NK90Z

STF5NK90Z
N-CHANNEL 900V - 2Ω - 4.5A TO-220/TO-220FP
Zener-Protected SuperMESH™MOSFET
Table 1: General Features Figure 1: Package
TYPE VDSS RDS(on) ID Pw
STP5NK90Z 900 V < 2.5 Ω 4.5 A 125 W
STF5NK90Z 900 V < 2.5 Ω 4.5 A (*) 30 W
■ TYPICAL RDS(on) = 2 Ω
■ EXTREMELY HIGH dv/dt CAPABILITY

■ IMPROVED ESD CAPABILITY

3
■ 100% AVALANCHE RATED 2
1
■ GATE CHARGE MINIMIZED

■ VERY LOW INTRINSIC CAPACITANCES

TO-220 TO-220FP
■ VERY GOOD MANUFACTURING

REPEATIBILITY
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DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established Figure 2: Internal Schematic Diagram
stripbased PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOS-
FETs including revolutionary MDmesh™ products.

APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-LINE POWER SUPPLIES,

ADAPTORS AND PFC

Table 2: Order Codes

SALES TYPE MARKING PACKAGE PACKAGING
STP5NK90Z P5NK90Z TO-220 TUBE
STF5NK90Z F5NK90Z TO-220FP TUBE

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Table 3: Absolute Maximum ratings

Symbol Parameter Value Unit
STP5NK90Z STF5NK90Z
VDS Drain-source Voltage (VGS = 0) 900 V
VDGR Drain-gate Voltage (RGS = 20 kΩ) 900 V
VGS Gate- source Voltage ± 30 V
ID Drain Current (continuous) at TC = 25°C 4.5 4.5 (*) A
ID Drain Current (continuous) at TC = 100°C 2.8 2.8 (*) A
IDM (
) Drain Current (pulsed) 18 18 (*) A
PTOT Total Dissipation at TC = 25°C 125 30 W
Derating Factor 1 0.24 W/°C
VESD(G-S) Gate source ESD(HBM-C=100pF, R=1.5KΩ) 4000 V
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
VISO Insulation Withstand Voltage (DC) - 2500 V
Tj Operating Junction Temperature -55 to 150 °C
Tstg Storage Temperature -55 to 150 °C
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(
) Pulse width limited by safe operating area
(1) ISD ≤4.5A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, T j ≤ T JMAX.
(*) Limited only by maximum temperature allowed

Table 4: Thermal Data

TO-220 TO-220FP
Rthj-case Thermal Resistance Junction-case Max 1 4.2 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
Tl Maximum Lead Temperature For Soldering Purpose 300 °C

Table 5: Avalanche Characteristics

Symbol Parameter Max Value Unit
IAR Avalanche Current, Repetitive or Not-Repetitive 4.5 A
(pulse width limited by Tj max)
EAS Single Pulse Avalanche Energy 230 mJ
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)

Table 6: Gate-Source Zener Diode

Symbol Parameter Test Conditions Min. Typ. Max. Unit
BVGSO Gate-Source Breakdown Igs=± 1mA (Open Drain) 30 V
Voltage

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.

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ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)

Table 7: On /Off
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source Breakdown ID = 1 mA, VGS = 0 900 V
Voltage
IDSS Zero Gate Voltage VDS = Max Rating 1 µA
Drain Current (VGS = 0) VDS = Max Rating, TC = 125°C 50 µA
IGSS Gate-body Leakage VGS = ± 20 V ± 10 µA
Current (VDS = 0)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 100 µA 3 3.75 4.5 V
RDS(on Static Drain-source On VGS = 10 V, ID = 2.25 A 2 2.5 Ω
Resistance

Table 8: Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit
gfs (1) Forward Transconductance VDS = 15 V , ID = 2.25 A 4.8 S
Ciss Input Capacitance VDS = 25 V, f = 1 MHz, VGS = 0 1160 pF
Coss Output Capacitance 105 pF
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Crss Reverse Transfer 21.5 pF
Capacitance
COSS eq (3). Equivalent Output VGS = 0 V, VDS = 0 to 720 V 65.5 pF
Capacitance
td(on) Turn-on Delay Time VDD = 450 V, ID = 2.2 A, 27 ns
tr Rise Time RG = 4.7 Ω, VGS = 10 V 7.2 ns
td(off) Turn-off-Delay Time (see Figure 19) 52 ns
tf Fall Time 19 ns
Qg Total Gate Charge VDD = 720 V, ID = 4.4 A, 41.5 58 nC
Qgs Gate-Source Charge VGS = 10 V 6.9 nC
Qgd Gate-Drain Charge (see Figure 22) 21.9 nC

Table 9: Source Drain Diode

Symbol Parameter Test Conditions Min. Typ. Max. Unit
ISD Source-drain Current 4.5 A
ISDM (2) Source-drain Current (pulsed) 18 A
VSD (1) Forward On Voltage ISD = 4.5 A, VGS = 0 1.6 V
trr Reverse Recovery Time ISD = 4.5 A, di/dt = 100 A/µs 518 ns
Qrr Reverse Recovery Charge VDD = 35V 3.2 µC
IRRM Reverse Recovery Current (see Figure 20) 12.2 A
trr Reverse Recovery Time ISD = 4.5 A, di/dt = 100 A/µs 712 ns
Qrr Reverse Recovery Charge VDD = 35V, Tj = 150°C 4.66 µC
IRRM Reverse Recovery Current (see Figure 20) 13.1 A
(1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(2) Pulse width limited by safe operating area.
(3) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.

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Figure 3: Safe Operating Area For TO-220 Figure 6: Thermal Impedance For TO-220

Figure 4: Safe Operating Area For TO-220FP Figure 7: Thermal Impedance For TO-220FP

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Figure 5: Output Characteristics Figure 8: Transfer Characteristics

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Figure 9: Transconductance Figure 12: Static Drain-source On Resistance

Figure 10: Gate Charge vs Gate-source Voltage Figure 13: Capacitance Variations

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Figure 11: Normalized Gate Threshold Voltage Figure 14: Normalized On Resistance vs Tem-
vs Temperature perature

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Figure 15: Source-Drain Forward Characteris- Figure 17: Avalanche Energy vs Starting Tj
tics

Figure 16: Normalized Breakdown Voltage vs

Temperature

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Figure 18: Unclamped Inductive Load Test Cir- Figure 21: Unclamped Inductive Wafeform
cuit

Figure 19: Switching Times Test Circuit For Figure 22: Gate Charge Test Circuit
Resistive Load
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Figure 20: Test Circuit For Inductive Load

Switching and Diode Recovery Times

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In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These
packages have a Lead-free second level interconnect . The category of second level interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an
ST trademark. ECOPACK specifications are available at: www.st.com

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TO-220FP MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 4.4 4.6 0.173 0.181
B 2.5 2.7 0.098 0.106
D 2.5 2.75 0.098 0.108
E 0.45 0.7 0.017 0.027
F 0.75 1 0.030 0.039
F1 1.15 1.7 0.045 0.067
F2 1.15 1.7 0.045 0.067
G 4.95 5.2 0.195 0.204
G1 2.4 2.7 0.094 0.106
H 10 10.4 0.393 0.409
L2 16 0.630
L3 28.6 30.6 1.126 1.204
L4 9.8 10.6 .0385 0.417
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L5 2.9 3.6 0.114 0.141
L6 15.9 16.4 0.626 0.645
L7 9 9.3 0.354 0.366
Ø 3 3.2 0.118 0.126

E
A

D
B

L3
L6
L7
F1

G1

G
H

F2

1 2 3
L5
L2 L4

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TO-220 MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
b 0.61 0.88 0.024 0.034
b1 1.15 1.70 0.045 0.066
c 0.49 0.70 0.019 0.027
D 15.25 15.75 0.60 0.620
E 10 10.40 0.393 0.409
e 2.40 2.70 0.094 0.106
e1 4.95 5.15 0.194 0.202
F 1.23 1.32 0.048 0.052
H1 6.20 6.60 0.244 0.256
J1 2.40 2.72 0.094 0.107
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L 13 14 0.511 0.551
L1 3.50 3.93 0.137 0.154
L20 16.40 0.645
L30 28.90 1.137
øP 3.75 3.85 0.147 0.151
Q 2.65 2.95 0.104 0.116

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Table 10: Revision History

Date Revision Description of Changes

24-Sep-2004 1 First release.
05-Oct-2004 2 Complete datasheet
06-Sep-2005 3 Inserted Ecopack indication

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