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    Dica Final Mid

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    pokiri_jus4u5873
    The document appears to be an exam for a Digital IC Applications course, containing 20 multiple choice questions covering topics like logic families (TTL, RTL, DTL), integrated circuits, CMOS logic, VHDL syntax and concepts (entity, architecture, package), and Verilog. It includes the student's information, date, time limit, and a signature line for the invigilator.

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    Dica Final Mid

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    pokiri_jus4u5873
    25 views2 pages
    The document appears to be an exam for a Digital IC Applications course, containing 20 multiple choice questions covering topics like logic families (TTL, RTL, DTL), integrated circuits, CMOS logic, VHDL syntax and concepts (entity, architecture, package), and Verilog. It includes the student's information, date, time limit, and a signature line for the invigilator.

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    The document appears to be an exam for a Digital IC Applications course, containing 20 multiple choice questions covering topics like logic families (TTL, RTL, DTL), integrated circuits, CMOS logic, VHDL syntax and concepts (entity, architecture, package), and Verilog. It includes the student's information, date, time limit, and a signature line for the invigilator.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    25 views2 pages

    Dica Final Mid

    Uploaded by

    pokiri_jus4u5873
    The document appears to be an exam for a Digital IC Applications course, containing 20 multiple choice questions covering topics like logic families (TTL, RTL, DTL), integrated circuits, CMOS logic, VHDL syntax and concepts (entity, architecture, package), and Verilog. It includes the student's information, date, time limit, and a signature line for the invigilator.

    Copyright:

    Attribution Non-Commercial (BY-NC)
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    Jagan’s College of Engineering & Technology Choutapalem::Nellore

    III Year B.Tech First Semester


    I mid Examinations, August – 2010

    DIGITAL IC APPLICATIONS (Objective)


    (Electronics and Communications Engineering)

    Hall Ticket No :
    Name of the student: Signature of invigilator:
    Signature of student: Date:

    Time:20 min Max Marks:20


    Answer all questions
    *****
    1. - - - - - - - as a voltage controlled resistance. [ ]
    a.TTL b.RTL c.DTL d.MOS

    2.Fabrication of components on a single chip [ ]


    a. Differentiated circuit b.integrated circuit
    c.multiplexer circuit d.logic circuit

    3. State 0 representing bit CMOS logic [ ]


    a.0-1.5v b.3.5-5.0v c.0-0.8v d.2.0-5.0v

    4. In Two input CMOS AND gate, no. of PMOS transistors are used are [ ]
    a.1 b.2 c.3 d.4

    5. When Vin of 5V is applied to the CMOS circuit PMOS is… NMOS is . [ ]


    a.OFF,OFF b.ON,ON c.OFF,ON d.ON,OFF

    6. The amount of time that the output of a logic circuit takes to change from one state
    to another state is called the ……………………. [ ]
    a.delay time b.propagation time c.transition time d.diffusion time

    7. From the following select the odd one [ ]


    a.system c b.verilog c.vhdl d.unix

    8. Following the keyword is not used for time dimension [ ]


    a.after b.wait on c.case d.wait for

    9. - - - - - - statement is preffered in data flow [ ]


    a.concurrent b.sequential c.process d.procedure

    10. Port is used in the following syntax [ ]


    a.architecture b.entity c.concurrent statements d.sequential statements
    11.In VHDL, V stands for - - - - - - - - - - [ ]
    a.VHS b.VSCI c.VHIC d.VHSIC

    12.In VHDL - - - - - is simply a declaration of a module inputs and outputs [ ]


    a.architecture b.dataflow c.entity d.behavioural

    13.Total no.of values presented in std_logic [ ]


    a.8 b.9 c.6 d.7

    14.IEEE.std_logic_1164.all,1164 represents…………………….. [ ]
    a.function b.procedure c.memory d.package

    15.port map is used in the following model [ ]


    a. Data flow b.behavioural c.structural d.variable

    16.component is used in the following model [ ]


    a.data flow b.structural c.behavioural d.constant

    17.assigning operator is used as [ ]


    a. /= b. < c. >= d. <=

    18.following statement is incorrect timedimension [ ]


    a.wait on data b.wait for 2ns; c.wait until clk=’1’ d.wait until A,B,C

    19.one of the following is not used for the mode (specify the signal direction) [ ]
    a.inout b.in c.variable d.out

    20.A VHDL ---------is a detailed description of modules internal structure or behavior [ ]


    a.signal b.architecture c.entity d.dataflow

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