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Y34NB50

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 STY34NB50F

N - CHANNEL 500V - 0.11Ω - 34 A - Max247


PowerMESH MOSFET
TYPE V DSS R DS(on) ID
STY34NB50F 500 V < 0.14 Ω 34 A
■ TYPICAL RDS(on) = 0.11 Ω
■ EXTREMELY HIGH dv/dt CAPABILITY
■ ± 30V GATE TO SOURCE VOLTAGE RATING
■ 100% AVALANCHE TESTED
■ LOW INTRINSIC CAPACITANCE
■ GATE CHARGE MINIMIZED
3
■ REDUCED VOLTAGE SPREAD 2
1
DESCRIPTION
Using the latest high voltage MESH OVERLAY Max247
process, STMicroelectronics has designed an ad-
vanced family of power MOSFETs with outstand-
ing performances. The new patent pending strip
layout coupled with the Company’s proprietary
edge termination structure, gives the lowest
RDS(on) per area, exceptional avalanche and INTERNAL SCHEMATIC DIAGRAM
dv/dt capabilities and unrivalled gate charge and
switching characteristics.

APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING

■ SWITCH MODE POWER SUPPLY (SMPS)

■ DC-AC CONVERTER FOR WELDING

EQUIPMENT AND UNINTERRUPTABLE


POWER SUPPLY AND MOTOR DRIVE

ABSOLUTE MAXIMUM RATINGS


Symb ol Parameter Value Un it
V DS Drain-source Voltage (VGS = 0) 500 V
V DGR Drain- gate Voltage (RGS = 20 kΩ) 500 V
V GS G ate-source Voltage ± 30 V
ID Drain Current (continuous) at Tc = 25 o C 34 A
ID Drain Current (continuous) at Tc = 100 o C 21.4 A
I DM (•) Drain Current (pulsed) 136 A
o
P tot T otal Dissipation at Tc = 25 C 450 W
o
Derating F actor 3.61 W/ C
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
o
T s tg Storage Temperature -65 to 150 C
o
Tj Max. O perating Junction Temperature 150 C
(•) Pulse width limited by safe operating area ( 1) ISD ≤34 A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX

December 1999 1/8


STY34NB50F

THERMAL DATA
o
R thj -case Thermal Resistance Junction-case Max 0.277 C/W
o
R thj -amb Thermal Resistance Junction-ambient Max 30 C/W
o
R thc-sink Thermal Resistance Case-sink Typ 0.1 C/W
o
Tl Maximum Lead Temperature F or Soldering Purpose 300 C

AVALANCHE CHARACTERISTICS
Symbo l Parameter Max Valu e Unit
IAR Avalanche Current, Repetitive or Not-Repetitive 34 A
(pulse width limited by Tj max)
E AS Single Pulse Avalanche Energy 1000 mJ
o
(starting Tj = 25 C, I D = IAR , VDD = 50 V)

ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)


OFF
Symbo l Parameter Test Con ditions Min. T yp. Max. Unit
V (BR)DSS Drain-source I D = 250 µA V GS = 0 500 V
Breakdown Voltage
I DSS Zero G ate Voltage V DS = Max Rating 10 µA
Drain Current (V GS = 0) V DS = Max Rating T c = 125 100 µA
o
C
IGSS Gate-body Leakage V GS = ± 30 V ± 100 nA
Current (VDS = 0)

ON (∗)
Symbo l Parameter Test Con ditions Min. T yp. Max. Unit
V GS(th) Gate Threshold V DS = V GS ID = 250 µA 3 4 5 V
Voltage
R DS(on) Static Drain-source O n V GS = 10 V I D = 17 A 0.11 0.14 Ω
Resistance
I D(o n) On State Drain Current V DS > ID(o n) x R DS(on )ma x 34 A
V GS = 10 V

DYNAMIC
Symbo l Parameter Test Con ditions Min. T yp. Max. Unit
g f s (∗) Forward V DS > ID(o n) x R DS(on )ma x I D = 17 A 27 S
Transconductance
C iss Input Capacitance V DS = 25 V f = 1 MHz V GS = 0 5.9 nF
C os s Output Capacitance 880 pF
C rss Reverse T ransfer 80 pF
Capacitance

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STY34NB50F

ELECTRICAL CHARACTERISTICS (continued)


SWITCHING ON
Symbo l Parameter Test Con ditions Min. T yp. Max. Unit
t d(on) Turn-on Time V DD = 250 V I D =17 A 45 ns
tr Rise Time R G = 4.7 Ω V GS =15 V 35 ns
(see test circuit, figure 3)
Qg Total Gate Charge V DD = 400 V ID = 34 A V GS = 10 V 140 196 nC
Q gs Gate-Source Charge 38 nC
Q gd Gate-Drain Charge 61 nC

SWITCHING OFF
Symbo l Parameter Test Con ditions Min. T yp. Max. Unit
tr (Voff) Off-voltage Rise Time V DD = 400 V I D = 17 A 28 ns
tf Fall Time R G = 4.7 Ω V GS = 15 V 30 ns
tc Cross-over Time (see test circuit, figure 5) 60 ns

SOURCE DRAIN DIODE


Symbo l Parameter Test Con ditions Min. T yp. Max. Unit
ISD Source-drain Current 34 A
I SDM (•) Source-drain Current 136 A
(pulsed)
V SD (∗) Forward On Voltage I SD = 34 A V GS = 0 1.6 V
t rr Reverse Recovery I SD = 34 A di/dt = 100 A/µs 715 ns
Time V DD = 100 V T j = 150 o C
Q rr Reverse Recovery (see test circuit, figure 5) 11.8 µC
Charge
I RRM Reverse Recovery 33 A
Current

(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %


(•) Pulse width limited by safe operating area

Safe Operating Area Thermal Impedance

3/8
STY34NB50F

Output Characteristics Transfer Characteristics

Transconductance Static Drain-source On Resistance

Gate Charge vs Gate-source Voltage Capacitance Variations

4/8
STY34NB50F

Normalized Gate Threshold Voltage vs Normalized On Resistance vs Temperature


Temperature

Source-drain Diode Forward Characteristics

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STY34NB50F

Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform

Fig. 3: Switching Times Test Circuits For Fig. 4: Gate Charge test Circuit
Resistive Load

Fig. 5: Test Circuit For Inductive Load Switching


And Diode Recovery Times

6/8
STY34NB50F

Max247 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 4.70 5.30

A1 2.20 2.60

b 1.00 1.40

b1 2.00 2.40

b2 3.00 3.40

c 0.40 0.80

D 19.70 20.30

e 5.35 5.55
E 15.30 15.90

L 14.20 15.20

L1 3.70 4.30

P025Q

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STY34NB50F

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are
subjec t to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics

 1999 STMicroelectronics – Printed in Italy – All Rights Reserved


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