Tja 1054

TJA1054
Fault-tolerant CAN transceiver

Rev. 4 — 3 August 2010 Product data sheet
1. General description
The TJA1054 is the interface between the protocol controller and the physical bus wires in
a Controller Area Network (CAN). It is primarily intended for low-speed applications up to
125 kBd in passenger cars. The device provides differential receive and transmit
capability but will switch to single-wire transmitter and/or receiver in error conditions.
The TJA1054T is pin and downwards compatible with the PCA82C252T and the
TJA1053T. This means that these two devices can be replaced by the TJA1054T with
retention of all functions.
The most important improvements of the TJA1054 with respect to the PCA82C252 and
TJA1053 are:
• Very low EME due to a very good matching of the CANL and CANH output signals
• Good EMI, especially in low power modes
• Full wake-up capability during bus failures
• Extended bus failure management including short-circuit of the CANH bus line to VCC
• Support for easy system fault diagnosis
• Two-edge sensitive wake-up input signal via pin WAKE
2. Features and benefits
2.1 Optimized for in-car low-speed communication

Baud rate up to 125 kBd
Up to 32 nodes can be connected
Supports unshielded bus wires
Very low ElectroMagnetic Emission (EME) due to built-in slope control function and a
very good matching of the CANL and CANH bus outputs
Very high ElectroMagnetic Immunity (EMI) in normal and low power operating modes
Fully integrated receiver filters
Transmit Data (TxD) dominant time-out function
2.2 Bus failure management

Supports single-wire transmission modes with ground offset voltages up to 1.5 V
Automatic switching to single-wire mode in the event of bus failures, even when the
CANH bus wire is short-circuited to VCC
Automatic reset to differential mode if bus failure is removed
Full wake-up capability during failure modes
NXP Semiconductors TJA1054
2.3 Protections
Bus pins short-circuit safe to battery and to ground
Thermally protected
Bus lines protected against transients in an automotive environment
An unpowered node does not disturb the bus lines
2.4 Support for low power modes

Low current sleep mode and standby mode with wake-up via the bus lines
Power-on reset flag on the output
3. Quick reference data

Table 1. Quick reference data
VCC = 4.75 V to 5.25 V; VBAT = 5.0 V to 27 V; VSTB = VCC; Tvj = −40 °C to +150 °C; all voltages are
defined with respect to ground; positive currents flow into the device; unless otherwise specified.[1][2]
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 4.75 - 5.25 V
VBAT battery supply voltage on no time limit −0.3 - +40 V
pin BAT operating mode [3] 5.0 - 27 V
load dump - - 40 V
IBAT battery supply current on sleep mode; VCC = 0 V; - 30 50 μA
pin BAT VBAT = 12 V
VCANH voltage on pin CANH VCC = 0 V to 5.0 V; −40 - +40 V
VBAT ≥ 0 V; no time limit;
with respect to
any other pin
VCANL voltage on pin CANL VCC = 0 V to 5.0 V; −40 - +40 V
VBAT ≥ 0 V; no time limit;
with respect to
any other pin
ΔVCANH voltage drop on pin CANH ICANH = −40 mA - - 1.4 V
ΔVCANL voltage drop on pin CANL ICANL = 40 mA - - 1.4 V
tPD(L) propagation delay TXD - 1 - μs
(LOW) to RXD (LOW)
tr bus line output rise time between 10 % and 90 %; - 0.6 - μs
C1 = 10 nF; see Figure 5
tf bus line output fall time between 10 % and 90 %; - 0.3 - μs
C1 = 1 nF; see Figure 5
Tvj virtual junction [4] −40 - +150 °C
temperature
[1] All parameters are guaranteed over the virtual junction temperature range by design, but only 100 % tested
at Tamb = 125 °C for dies on wafer level, and above this for cased products 100 % tested at Tamb = 25 °C,
unless otherwise specified.
[2] For bare die, all parameters are only guaranteed if the back side of the die is connected to ground.
[3] A local or remote wake-up event will be signalled at the transceiver pins RXD and ERR if
VBAT = 5.3 V to 27 V see Table 5.
TJA1054 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 3 August 2010 2 of 25

[4] Junction temperature in accordance with “IEC 60747-1”. An alternative definition is: Tvj = Tamb + P × Rth(vj-a)
where Rth(vj-a) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable
combinations of power dissipation (P) and ambient temperature (Tamb).
4. Ordering information
Table 2. Ordering information
Type number Package
Name Description Version
TJA1054T SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
TJA1054T/S900 SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
TJA1054U - bare die; 1990 × 2700 × 375 μm -
5. Block diagram
BAT VCC
14 10
1
INH
7 TEMPERATURE
WAKE WAKE-UP PROTECTION
5 STANDBY
STB CONTROL 9
6 RTL
EN 11
CANH
VCC 12
CANL
8
2 DRIVER RTH
TXD TIMER
VCC TJA1054
FAILURE DETECTOR
4
ERR PLUS WAKE-UP
PLUS TIME-OUT
VCC FILTER
RECEIVER
3
RXD
FILTER
13 mgl421
GND
Fig 1. Block diagram

6. Pinning information
6.1 Pinning
INH 1 14 BAT
TXD 2 13 GND
RXD 3 12 CANL
ERR 4 TJA1054T 11 CANH
STB 5 10 VCC
EN 6 9 RTL
WAKE 7 8 RTH
001aaf610
Fig 2. Pin configuration
6.2 Pin description

Table 3. Pin description
Symbol Pin Description
INH 1 inhibit output for switching an external voltage regulator if a
wake-up signal occurs
TXD 2 transmit data input for activating the driver to the bus lines
RXD 3 receive data output for reading out the data from the bus lines
ERR 4 error, wake-up and power-on indication output; active LOW in
normal operating mode when a bus failure is detected; active LOW
in standby and sleep mode when a wake-up is detected; active
LOW in power-on standby when a VBAT power-on event is
detected
STB 5 standby digital control signal input; together with the input signal
on pin EN this input determines the state of the transceiver;
see Table 5 and Figure 3
EN 6 enable digital control signal input; together with the input signal on
pin STB this input determines the state of the transceiver;
see Table 5 and Figure 3
WAKE 7 local wake-up signal input (active LOW); both falling and rising
edges are detected
RTH 8 termination resistor connection; in case of a CANH bus wire error
the line is terminated with a predefined impedance
RTL 9 termination resistor connection; in case of a CANL bus wire error
the line is terminated with a predefined impedance
VCC 10 supply voltage
CANH 11 HIGH-level CAN bus line
CANL 12 LOW-level CAN bus line
GND 13 ground
BAT 14 battery supply voltage

7. Functional description
The TJA1054 is the interface between the CAN protocol controller and the physical wires
of the CAN bus (see Figure 7). It is primarily intended for low-speed applications, up to
125 kBd, in passenger cars. The device provides differential transmit capability to the
CAN bus and differential receive capability to the CAN controller.
To reduce EME, the rise and fall slopes are limited. This allows the use of an unshielded
twisted pair or a parallel pair of wires for the bus lines. Moreover, the device supports
transmission capability on either bus line if one of the wires is corrupted. The failure
detection logic automatically selects a suitable transmission mode.
In normal operating mode (no wiring failures) the differential receiver is output on pin RXD
(see Figure 1). The differential receiver inputs are connected to pins CANH and CANL
through integrated filters. The filtered input signals are also used for the single-wire
receivers. The receivers connected to pins CANH and CANL have threshold voltages that
ensure a maximum noise margin in single-wire mode.
A timer function (TxD dominant time-out function) has been integrated to prevent the bus
lines from being driven into a permanent dominant state (thus blocking the entire network
communication) due to a situation in which pin TXD is permanently forced to a LOW level,
caused by a hardware and/or software application failure.
If the duration of the LOW level on pin TXD exceeds a certain time, the transmitter will be
disabled. The timer will be reset by a HIGH level on pin TXD.
7.1 Failure detector

The failure detector is fully active in the normal operating mode. After the detection of a
single bus failure the detector switches to the appropriate mode (see Table 4). The
differential receiver threshold voltage is set at −3.2 V typical (VCC = 5 V). This ensures
correct reception with a noise margin as high as possible in the normal operating mode
and in the event of failures 1, 2, 5 and 6a. These failures, or recovery from them, do not
destroy ongoing transmissions. The output drivers remain active, the termination does not
change and the receiver remains in differential mode (see Table 4).
Failures 3, 3a and 6 are detected by comparators connected to the CANH and CANL bus
lines. Failures 3 and 3a are detected in a two-step approach. If the CANH bus line
exceeds a certain voltage level, the differential comparator signals a continuous dominant
condition. Because of inter operability reasons with the predecessor products
PCA82C252 and TJA1053, after a first time-out the transceiver switches to single-wire
operation through CANH. If the CANH bus line is still exceeding the CANH detection
voltage for a second time-out, the TJA1054 switches to CANL operation; the CANH driver
is switched off and the RTH bias changes to the pull-down current source. The time-outs
(delays) are needed to avoid false triggering by external RF fields.

Table 4. Bus failures

Failure Description Termination Termination CANH CANL Receiver
CANH (RTH) CANL (RTL) driver driver mode
1 CANH wire on on on on differential
interrupted
2 CANL wire interrupted on on on on differential
3 CANH short-circuited weak[1] on off on CANL
to battery
3a CANH short-circuited weak[1] on off on CANL
to VCC
4 CANL short-circuited on weak[2] on off CANH
to ground
5 CANH short-circuited on on on on differential
to ground
6 CANL short-circuited on weak[2] on off CANH
to battery
6a CANL short-circuited on on on on differential
to VCC
7 CANL and CANH on weak[2] on off CANH
mutually
short-circuited
[1] A weak termination implies a pull-down current source behavior of 75 μA typical.

[2] A weak termination implies a pull-up current source behavior of 75 μA typical.
Failure 6 is detected if the CANL bus line exceeds its comparator threshold for a certain
period of time. This delay is needed to avoid false triggering by external RF fields. After
detection of failure 6, the reception is switched to the single-wire mode through CANH;
the CANL driver is switched off and the RTL bias changes to the pull-up current source.
Recovery from failures 3, 3a and 6 is detected automatically after reading a consecutive

recessive level by corresponding comparators for a certain period of time.
Failures 4 and 7 initially result in a permanent dominant level on pin RXD. After a time-out
the CANL driver is switched off and the RTL bias changes to the pull-up current source.
Reception continues by switching to the single-wire mode via pins CANH or CANL. When
failures 4 or 7 are removed, the recessive bus levels are restored. If the differential
voltage remains below the recessive threshold level for a certain period of time, reception
and transmission switch back to the differential mode.
If any of the wiring failure occurs, the output signal on pin ERR will be set to LOW. On
error recovery, the output signal on pin ERR will be set to HIGH again. In case of an
interrupted open bus wire, this failure will be detected and signalled only if there is an
open wire between the transmitting and receiving node(s). Thus, during open wire
failures, pin ERR typically toggles.
During all single-wire transmissions, EMC performance (both immunity and emission) is
worse than in the differential mode. The integrated receiver filters suppress any HF noise
induced into the bus wires. The cut-off frequency of these filters is a compromise between
propagation delay and HF suppression. In single-wire mode, LF noise cannot be
distinguished from the required signal.

7.2 Low power modes

The transceiver provides three low power modes which can be entered and exited via
STB and EN (see Table 5 and Figure 3).
The sleep mode is the mode with the lowest power consumption. Pin INH is switched to
HIGH-impedance for deactivation of the external voltage regulator. Pin CANL is biased to
the battery voltage via pin RTL. If the supply voltage is provided, pins RXD and ERR will
signal the wake-up interrupt.
The standby mode operates in the same way as the sleep mode but with a HIGH level on
pin INH.
The power-on standby mode is the same as the standby mode, however, in this mode the
battery power-on flag is shown on pin ERR instead of the wake-up interrupt signal. The
output on pin RXD will show the wake-up interrupt. This mode is only for reading out the
power-on flag.
Table 5. Normal operating and low power modes

Mode Pin STB Pin EN Pin ERR Pin RXD Pin RTL
LOW HIGH LOW HIGH switched
to
Goto-sleep LOW HIGH wake-up wake-up VBAT
command interrupt interrupt
Sleep LOW LOW[4] signal[1][2][3] signal[1][2][3]
Standby LOW LOW

Power-on HIGH LOW VBAT wake-up VBAT
standby power-on interrupt
flag[1][5] signal[1][2][3]
Normal HIGH HIGH error flag no error dominant recessive VCC
operating flag received received
data data
[1] If the supply voltage VCC is present

[2] Wake-up interrupts are released when entering normal operating mode.
[3] A local or remote wake-up event will be signalled at the transceiver pins RXD and ERR if
VBAT = 5.3 V to 27 V.
[4] In case the goto-sleep command was used before. When VCC drops, pin EN will become LOW, but due to
the fail-safe functionality this does not effect the internal functions.
[5] VBAT power-on flag will be reset when entering normal operating mode.
Wake-up requests are recognized by the transceiver through two possible channels:
• The bus lines for remote wake-up

• Pin WAKE for local wake-up
In order to wake-up the transceiver remotely through the bus lines, a filter mechanism is
integrated. This mechanism makes sure that noise and any present bus failure conditions
do not result into an erroneous wake-up. Because of this mechanism it is not sufficient to
simply pull the CANH or CANL bus lines to a dominant level for a certain time. To
guarantee a successful remote wake-up under all conditions, a message frame with a
dominant phase of at least the maximum specified t(CANH) or t(CANL) in it is required.

A local wake-up through pin WAKE is detected by a rising or falling edge with a
consecutive level exceeding the maximum specified tWAKE.
On a wake-up request the transceiver will set the output on pin INH to HIGH which can be
used to activate the external supply voltage regulator.
If VCC is provided the wake-up request can be read on the ERR or RXD outputs, so the
external microcontroller can activate the transceiver (switch to normal operating mode) via
pins STB and EN.
To prevent a false remote wake-up due to transients or RF fields, the wake-up voltage
levels have to be maintained for a certain period of time. In the low power modes the
failure detection circuit remains partly active to prevent an increased power consumption
in the event of failures 3, 3a, 4 and 7.
To prevent a false local wake-up during an open wire at pin WAKE, this pin has a weak
pull-up current source towards VBAT. However, in order to prevent EMC issues, it is
recommended to connect a not used pin WAKE to pin BAT. INH is set to floating only if
the goto-sleep command is entered successfully. To enter a successful goto-sleep
command under all conditions, this command must be kept stable for the maximum
specified th(sleep).
Pin INH will be set to a HIGH level again by the following events only:
• VBAT power-on (cold start)

• Rising or falling edge on pin WAKE
• A message frame with a dominant phase of at least the maximum specified t(CANH) or
t(CANL), while pin EN or pin STB is at a LOW level
• Pin STB goes to a HIGH level with VCC active
To provide fail-safe functionality, the signals on pins STB and EN will internally be set to
LOW when VCC is below a certain threshold voltage (VCC(stb)).
7.3 Power-on
After power-on (VBAT switched on) the signal on pin INH will become HIGH and an internal
power-on flag will be set. This flag can be read in the power-on standby mode through
pin ERR (STB = 1; EN = 0) and will be reset by entering the normal operating mode.
7.4 Protections
A current limiting circuit protects the transmitter output stages against short-circuit to
positive and negative battery voltage.
If the junction temperature exceeds the typical value of 165 °C, the transmitter output
stages are disabled. Because the transmitter is responsible for the major part of the power
dissipation, this will result in a reduced power dissipation and hence a lower chip
temperature. All other parts of the device will continue to operate.
The pins CANH and CANL are protected against electrical transients which may occur in
an automotive environment.

POWER-ON
STANDBY
10
GOTO
NORMAL (4) SLEEP (5)
11 01
(1) STANDBY SLEEP

00 00
(2)
(3)
mbk949
Mode 10 stands for: Pin STB = HIGH and pin EN = LOW.

(1) Mode change via input pins STB and EN.
(2) Mode change via input pins STB and EN; it should be noted that in the sleep mode pin INH is
inactive and possibly there is no VCC. Mode control is only possible if VCC of the transceiver is
active.
(3) Pin INH is activated after wake-up via bus input pin WAKE.
(4) Transitions to normal mode clear the internal wake-up: interrupt and battery fail flag are
cleared.
(5) Transitions to sleep mode: pin INH is deactivated.
Fig 3. Mode control
8. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.3 +6 V
VBAT battery supply voltage −0.3 +40 V
VTXD voltage on pin TXD −0.3 VCC + 0.3 V
VRXD voltage on pin RXD −0.3 VCC + 0.3 V
VERR voltage on pin ERR −0.3 VCC + 0.3 V
VSTB voltage on pin STB −0.3 VCC + 0.3 V
VEN voltage on pin EN −0.3 VCC + 0.3 V
VCANH voltage on pin CANH with respect to any −40 +40 V
other pin
VCANL voltage on pin CANL with respect to any −40 +40 V
other pin
Vtrt(n) transient voltage on see Figure 6 −150 +100 V
pins CANH and CANL

Table 6. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
VI(WAKE) input voltage on pin WAKE with respect to any − VBAT + 0.3 V
other pin
II(WAKE) input current on pin WAKE [2] −15 - mA
VINH voltage on pin INH −0.3 VBAT + 0.3 V
VRTH voltage on pin RTH with respect to any −0.3 VBAT + 1.2 V
other pin
VRTL voltage on pin RTL with respect to any −0.3 VBAT + 1.2 V
other pin
RRTH termination resistance on 500 16000 Ω
pin RTH
RRTL termination resistance on 500 16000 Ω
pin RTL
Tvj virtual junction temperature [3] −40 +150 °C
Tstg storage temperature −55 +150 °C
VESD electrostatic discharge human body model [4] −2 +2 kV
voltage machine model [5] −100 +100 V
[1] All voltages are defined with respect to pin GND, unless otherwise specified. Positive current flows into the
device.
[2] Only relevant if VWAKE < VGND − 0.3 V; current will flow into pin GND.
[3] Junction temperature in accordance with “IEC 60747-1”. An alternative definition is: Tvj = Tamb + P × Rth(vj-a)
where Rth(vj-a) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable
combinations of power dissipation (P) and ambient temperature (Tamb).
[4] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.
[5] Equivalent to discharging a 200 pF capacitor through a 10 Ω resistor and a 0.75 μH coil.
9. Thermal characteristics
Table 7. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient in free air 120 K/W
Rth(j-s) thermal resistance from junction to substrate in free air 40 K/W
bare die

10. Static characteristics

Table 8. Static characteristics
VCC = 4.75 V to 5.25 V; VBAT = 5.0 V to 27 V; VSTB = VCC; Tvj = −40 °C to +150 °C; all voltages are defined with respect to
ground; positive currents flow into the device; unless otherwise specified.[1][2][3]
Supplies (pins VCC and BAT)
VCC supply voltage 4.75 - 5.25 V
VCC(stb) supply voltage for forced 2.75 - 4.5 V
standby mode (fail-safe)
ICC supply current normal operating mode; 4 7 11 mA
VTXD = VCC (recessive)
normal operating mode; 10 17 27 mA
VTXD = 0 V (dominant); no load
low power modes at VTXD = VCC 0 0 10 μA
VBAT battery supply voltage no time limit −0.3 - +40 V
on pin BAT operating mode 5.0 - 27 V
load dump - - 40 V
IBAT battery supply current all modes and in low power
on pin BAT modes at
VRTL = VWAKE = VINH = VBAT
VBAT = 12 V 10 30 50 μA
VBAT = 5 V to 27 V 5 30 125 μA
VBAT = 3.5 V 5 20 30 μA
VBAT = 1 V 0 0 10 μA
sleep mode; VCC = 0 V;
VBAT = 12 V - 30 50 μA
VBAT(Pwon) power-on flag voltage low power modes
on pin BAT power-on flag set - - 1 V
power-on flag not set 3.5 - - V
Itot supply current plus low power modes; VCC = 5 V; - 30 60 μA
battery current VBAT = VWAKE = VINH = 12 V
Pins STB, EN and TXD
VIH HIGH-level input voltage 0.7VCC - VCC +0.3 V
VIL LOW-level input voltage −0.3 - 0.3VCC V
IIH HIGH-level input current
pins STB and EN VI = 4 V - 9 20 μA
pin TXD VI = 4 V −200 −80 −25 μA
IIL LOW-level input current
pins STB and EN VI = 1 V 4 8 - μA
pin TXD VI = 1 V −800 −320 −100 μA

Table 8. Static characteristics …continued

Pins RXD and ERR
VOH) HIGH-level output
voltage
on pin ERR IO = −100 μA VCC − 0.9 - VCC V
on pin RXD IO = −1 mA VCC − 0.9 - VCC V
VOL LOW-level output
voltage
on pin ERR IO = 1.6 mA 0 - 0.4 V
on pin RXD IO = 7.5 mA 0 - 1.5 V
Pin WAKE
IIL LOW-level input current VWAKE = 0 V; VBAT = 27 V −10 −4 −1 μA
Vth(wake) wake-up threshold VSTB = 0 V 2.5 3.2 3.9 V
voltage
Pin INH
ΔVH HIGH-level voltage drop IINH = −0.18 mA - - 0.8 V
IL leakage current sleep mode; VINH = 0 V - - 5 μA
Pins CANH and CANL
VCANH voltage on pin CANH VCC = 0 V to 5.0 V; VBAT ≥ 0 V; −40 - +40 V
no time limit; with respect to
any other pin
VCANL voltage on pin CANL VCC = 0 V to 5.0 V; VBAT ≥ 0 V; −40 - +40 V
no time limit; with respect to
any other pin
ΔVCANH voltage drop on pin ICANH = −40 mA - - 1.4 V
CANH
ΔVCANL voltage drop on pin ICANL = 40 mA - - 1.4 V
CANL
Vth(dif) differential receiver no failures and
threshold voltage bus failures 1, 2, 5 and 6a;
see Figure 4
VCC = 5 V −3.5 −3.2 −2.9 V
VCC = 4.75 V to 5.25 V −0.70VCC −0.64VCC −0.58VCC V
VO(reces) recessive output voltage VTXD = VCC
on pin CANH RRTH < 4 kΩ - - 0.2 V
on pin CANL RRTL < 4 kΩ VCC − 0.2 - - V
VO(dom) dominant output voltage VTXD = 0 V; VEN = VCC
on pin CANH ICANH = −40 mA VCC − 1.4 - - V
on pin CANL ICANL = 40 mA - - 1.4 V
IO(CANH) output current on normal operating mode; −110 −80 −45 mA
pin CANH VCANH = 0 V; VTXD = 0 V
low power modes; - −0.25 - μA
VCANH = 0 V; VCC = 5 V


IO(CANL) output current on normal operating mode; 45 70 100 mA
pin CANL VCANL = 14 V; VTXD = 0 V
low power modes; - 0 - μA
VCANL = 12 V; VBAT = 12 V
Vd(CANH)(sc) detection voltage for normal operating mode; 1.5 1.7 1.85 V
short-circuit to battery VCC = 5 V
voltage on pin CANH low power modes 1.1 1.8 2.5 V
Vd(CANL)(sc) detection voltage for normal operating mode
short-circuit to battery VCC = 5 V 6.6 7.2 7.8 V
voltage on pin CANL
VCC = 4.75 V to 5.25 V 1.32VCC 1.44VCC 1.56VCC V
Vth(wake) wake-up threshold
voltage
on pin CANL low power modes 2.5 3.2 3.9 V
on pin CANH low power modes 1.1 1.8 2.5 V
ΔVth(wake) difference of wake-up low power modes 0.8 1.4 - V
threshold voltages
Vth(CANH)(sc) single-ended receiver normal operating mode and
threshold voltage on failures 4, 6 and 7
pin CANH VCC = 5 V 1.5 1.7 1.85 V
Vth(CANL)(sc) single-ended receiver normal operating mode and
threshold voltage on failures 3 and 3a
pin CANL VCC = 5 V 3.15 3.3 3.45 V
Ri(CANH)(sc) single-ended input normal operating mode 110 165 270 kΩ
resistance on pin CANH
Ri(CANL)(sc) single-ended input normal operating mode 110 165 270 kΩ
resistance on pin CANL
Ri(dif) differential input normal operating mode 220 330 540 kΩ
resistance
Pins RTH and RTL
Rsw(RTL) switch-on resistance on normal operating mode; - 50 100 Ω
pin RTL and VCC |IO| < 10 mA
Rsw(RTH) switch-on resistance on normal operating mode; - 50 100 Ω
pin RTH and ground |IO| < 10 mA
VO(RTH) output voltage on low power modes; IO = 1 mA - 0.7 1.0 V
pin RTH
IO(RTL) output current on low power modes; VRTL = 0 V −1.25 −0.65 −0.3 mA
pin RTL
Ipu(RTL) pull-up current on normal operating mode and - 75 - μA
pin RTL failures 4, 6 and 7


Ipd(RTH) pull-down current on normal operating mode and - 75 - μA
pin RTH failures 3 and 3a
Thermal shutdown
Tj(sd) shutdown junction 155 165 180 °C
temperature
[1] All parameters are guaranteed over the virtual junction temperature range by design, but only 100 % tested at Tamb = 125 °C for dies on
wafer level, and above this for cased products 100 % tested at Tamb = 25 °C, unless otherwise specified.
[3] A local or remote wake-up event will be signalled at the transceiver pins RXD and ERR if VBAT = 5.3 V to 27 V (see Table 5).
11. Dynamic characteristics

Table 9. Dynamic characteristics
ground; unless otherwise specified.[1][2][3]
tt(r-d) transition time for between 10 % and 90 %; R1 = 100 Ω; 0.35 0.65 - μs
recessive to dominant (on C1 = 10 nF; C2 = not present;
pins CANL and CANH) see Figure 5
tt(d-r)) transition time for dominant between 10 % and 90 %; R1 = 100 Ω; 0.2 0.3 - μs
to recessive (on pins CANL C1 = 10 nF; C2 = not present;
and CANH) see Figure 5
tPD(L) propagation delay TXD no failures and failures 1, 2, 5 and 6a;
(LOW) to RXD (LOW) R1 = 100 Ω; see Figure 4 and Figure 5
C1 = 1 nF; C2 = not present - 0.75 1.5 μs
C1 = C2 = 3.3 nF - 1 1.75 μs
failures 3, 3a, 4, 6 and 7; R1 = 100 Ω;
see Figure 4 and Figure 5
C1 = C2 = 3.3 nF - 1.1 1.7 μs
tPD(H) propagation delay TXD no failures and failures 1, 2, 5 and 6a;
(HIGH) to RXD (HIGH) R1 = 100 Ω; see Figure 4 and Figure 5
C1 = C2 = 3.3 nF - 2.5 3.3 μs
failures 3, 3a, 4, 6 and 7; R1 = 100 Ω;
see Figure 4 and Figure 5
C1 = C2 = 3.3 nF - 1.5 2.2 μs
tr bus line output rise time between 10 % and 90 %; C1 = 10 nF; - 0.6 - μs
see Figure 5
tf bus line output fall time between 10 % and 90 %; C1 = 1 nF; - 0.3 - μs
see Figure 5
treact(sleep) reaction time of goto sleep [4] 5 - 50 μs
command

Table 9. Dynamic characteristics …continued

ground; unless otherwise specified.[1][2][3]
tdis(TxD) disable time of TxD normal operating mode; VTXD = 0 V 0.75 - 4 ms
permanent dominant timer
tCANH dominant time for remote low power modes; VBAT = 12 V [4] 7 - 38 μs
wake-up on pin CANH
tCANL dominant time for remote low power modes; VBAT = 12 V [4] 7 - 38 μs
wake-up on pin CANL
tWAKE required time on pin low power modes; VBAT = 12 V; for [4] 7 - 38 μs
WAKE for local wake-up wake-up after receiving a falling or
rising edge
tdet failure detection time normal operating mode
failures 3 and 3a 1.6 - 8.0 ms
failures 4, 6 and 7 0.3 - 1.6 ms
low power modes; VBAT = 12 V
failures 4 and 7 0.1 - 1.6 ms
trec failure recovery time normal operating mode
failures 4 and 7 7 - 38 μs
failure 6 125 - 750 μs
low power modes; VBAT = 12 V
failures 3, 3a, 4 and 7 0.3 - 1.6 ms
ndet pulse-count difference normal operating mode and - 4 -
between CANH and CANL failures 1, 2, 5 and 6a;
for failure detection pin ERR becomes LOW
nrec number of consecutive failures 1, 2, 5 and 6a - 4 -
pulses on CANH and
CANL simultaneously for
failure recovery
[1] All parameters are guaranteed over the virtual junction temperature range by design, but only 100 % tested at Tamb = 125 °C for dies on
wafer level, and above this for cased products 100 % tested at Tamb = 25 °C, unless otherwise specified.
[3] A local or remote wake-up event will be signalled at the transceiver pins RXD and ERR if VBAT = 5.3 V to 27 V (see Table 5).
[4] To guarantee a successful mode transition under all conditions, the maximum specified time must be applied.

VTXD VCC
0V
VCANL 5V
3.6 V
1.4 V
VCANH 0V
2.2 V
−3.2 V
ΔVCAN −5 V
VRXD
0.7VCC
0.3VCC
tPD(L) tPD(H) 015aaa175
Vdiff = VCANH − VCANL

Fig 4. Timing diagram for dynamic characteristics
12. Test information
+5 V
INH BAT VCC

1 14 10 R1 C1
WAKE RTH
7 8
TXD
2 CANL
12
STB
5 TJA1054 C2
CANH
EN 11
6
RXD RTL
3 9
R1 C1
13 4
20 pF GND ERR
mgl423
Termination resistors R1 (100 Ω) are not connected to pin RTH or pin RTL for testing purposes
because the minimum load allowed on the CAN bus lines is 500 Ω per transceiver.
The capacitive bus load of 10 nF is split into 3 equal capacitors (3.3 nF) to simulate the bus
cable.
Fig 5. Test circuit for dynamic characteristics

+12 V
+5 V
10 μF
INH BAT VCC

1 14 10 125 Ω 1 nF
WAKE RTH
7 8
TXD 511 Ω
2 CANL
12
STB 1 nF
5 TJA1054 GENERATOR
CANH
EN 11
6 1 nF
511 Ω
RXD RTL
3 9
125 Ω 1 nF
13 4
20 pF
GND ERR
mgl426
The waveforms of the applied transients on pins CANH and CANL will be in accordance with
ISO 7637 part 1: test pulses 1, 2, 3a and 3b.
Fig 6. Test circuit for automotive transients
VBAT
BATTERY
VDD +5 V
P8xC592/P8xCE598
CAN CONTROLLER
+5 V
CTX0 CRXO Px.x Px.x Px.x
TXD RXD STB ERR EN INH

2 3 5 4 6 1
WAKE BAT
7 14
TJA1054 VCC
10
CAN TRANSCEIVER
100 nF
GND
13
8 11 12 9
RTH CANH CANL RTL
CAN BUS LINE

mgl425
Fig 7. Application diagram
12.1 Quality information

This product has been qualified to the appropriate Automotive Electronics Council (AEC)
standard Q100 or Q101 and is suitable for use in automotive applications.

13. Bare die information

Table 10. Bonding pad locations
Symbol Pad Coordinates[1]
x y
INH 1 106 317
TXD 2 111 169
RXD 3 750 111
ERR 4 1347 111
STB 5 2248 103
EN 6 2521 240
WAKE 7 2521 381
RTH 8 2550 1269
RTL 9 2359 1840
VCC 10 1886 1809
CANH 11 872 1840
CANL 12 437 1840
GND 13a 80 1356
GND 13b 80 1241
BAT 14 106 772
[1] All coordinates (μm) represent the position of the center of each pad with respect to the bottom left-hand
corner of the top aluminium layer (see Figure 8).
12 11 10 9
13a
13b 8
1990
μm TJA1054U
14
7
1
6
2
3 4 5
x 0
0
y 2700 μm
mgw505
Fig 8. Bonding pad locations

14. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
D E A
X
y HE v M A
14 8
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 7 L
e w M detail X
bp
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 o
0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8
o
0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
99-12-27
SOT108-1 076E06 MS-012
03-02-19
Fig 9. Package outline SOT108-1 (SO14)


15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
15.3 Wave soldering

Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities

15.4 Reflow soldering

Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 10) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 11 and 12
Table 11. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 ≥ 350
< 2.5 235 220
≥ 2.5 220 220
Table 12. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 10.

maximum peak temperature

temperature = MSL limit, damage level
minimum peak temperature

= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level

Fig 10. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.
16. Revision history

Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TJA1054 v.4 20100803 Product data sheet - TJA1054_3
Modifications: • The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Value of parameter VESD (machine model) changed in Table 6.
• Typing error corrected in Table 8 in the conditions column for IBAT.
TJA1054_3 20040323 Product specification - TJA1054_2
(9397 750 11721)
TJA1054_2 20011120 Product specification - TJA1054_1
(9397 750 08965)
TJA1054_1 19990211 Preliminary specification - -
(9397 750 03636)

17. Legal information
17.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
Draft — The document is a draft version only. The content is still under
NXP Semiconductors products in such equipment or applications and
internal review and subject to formal approval, which may result in
therefore such inclusion and/or use is at the customer’s own risk.
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of Applications — Applications that are described herein for any of these
information included herein and shall have no liability for the consequences of products are for illustrative purposes only. NXP Semiconductors makes no
use of such information. representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended Customers are responsible for the design and operation of their applications
for quick reference only and should not be relied upon to contain detailed and and products using NXP Semiconductors products, and NXP Semiconductors
full information. For detailed and full information see the relevant full data accepts no liability for any assistance with applications or customer product
sheet, which is available on request via the local NXP Semiconductors sales design. It is customer’s sole responsibility to determine whether the NXP
office. In case of any inconsistency or conflict with the short data sheet, the Semiconductors product is suitable and fit for the customer’s applications and
full data sheet shall prevail. products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
Product specification — The information and data provided in a Product design and operating safeguards to minimize the risks associated with their
data sheet shall define the specification of the product as agreed between applications and products.
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however, NXP Semiconductors does not accept any liability related to any default,
shall an agreement be valid in which the NXP Semiconductors product is damage, costs or problem which is based on any weakness or default in the
deemed to offer functions and qualities beyond those described in the customer’s applications or products, or the application or use by customer’s
Product data sheet. third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
17.3 Disclaimers the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limited warranty and liability — Information in this document is believed to Limiting values — Stress above one or more limiting values (as defined in
be accurate and reliable. However, NXP Semiconductors does not give any the Absolute Maximum Ratings System of IEC 60134) will cause permanent
representations or warranties, expressed or implied, as to the accuracy or damage to the device. Limiting values are stress ratings only and (proper)
completeness of such information and shall have no liability for the operation of the device at these or any other conditions above those given in
consequences of use of such information. the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
In no event shall NXP Semiconductors be liable for any indirect, incidental,
repeated exposure to limiting values will permanently and irreversibly affect
punitive, special or consequential damages (including - without limitation - lost
the quality and reliability of the device.
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such Terms and conditions of commercial sale — NXP Semiconductors
damages are based on tort (including negligence), warranty, breach of products are sold subject to the general terms and conditions of commercial
contract or any other legal theory. sale, as published at http://www.nxp.com/profile/terms, unless otherwise
Notwithstanding any damages that customer might incur for any reason agreed in a valid written individual agreement. In case an individual
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards agreement is concluded only the terms and conditions of the respective
customer for the products described herein shall be limited in accordance agreement shall apply. NXP Semiconductors hereby expressly objects to
with the Terms and conditions of commercial sale of NXP Semiconductors. applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without No offer to sell or license — Nothing in this document may be interpreted or
limitation specifications and product descriptions, at any time and without construed as an offer to sell products that is open for acceptance or the grant,
notice. This document supersedes and replaces all information supplied prior conveyance or implication of any license under any copyrights, patents or
to the publication hereof. other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed, Export control — This document as well as the item(s) described herein
authorized or warranted to be suitable for use in life support, life-critical or may be subject to export control regulations. Export might require a prior
safety-critical systems or equipment, nor in applications where failure or authorization from national authorities.

Bare die — All die are tested on compliance with their related technical All die sales are conditioned upon and subject to the customer entering into a
specifications as stated in this data sheet up to the point of wafer sawing and written die sale agreement with NXP Semiconductors through its legal
are handled in accordance with the NXP Semiconductors storage and department.
transportation conditions. If there are data sheet limits not guaranteed, these
Quick reference data — The Quick reference data is an extract of the
will be separately indicated in the data sheet. There are no post-packing tests
product data given in the Limiting values and Characteristics sections of this
performed on individual die or wafers.
document, and as such is not complete, exhaustive or legally binding.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or 17.4 Trademarks
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in Notice: All referenced brands, product names, service names and trademarks
which the die is used. are the property of their respective owners.
18. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

19. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
2.1 Optimized for in-car low-speed
communication . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 Bus failure management. . . . . . . . . . . . . . . . . . 1
2.3 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.4 Support for low power modes . . . . . . . . . . . . . . 2
3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 5
7.1 Failure detector. . . . . . . . . . . . . . . . . . . . . . . . . 5
7.2 Low power modes . . . . . . . . . . . . . . . . . . . . . . 7
7.3 Power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.4 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9
9 Thermal characteristics . . . . . . . . . . . . . . . . . 10
10 Static characteristics. . . . . . . . . . . . . . . . . . . . 11
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 14
12 Test information . . . . . . . . . . . . . . . . . . . . . . . . 16
12.1 Quality information . . . . . . . . . . . . . . . . . . . . . 17
13 Bare die information . . . . . . . . . . . . . . . . . . . . 18
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
15 Soldering of SMD packages . . . . . . . . . . . . . . 20
15.1 Introduction to soldering . . . . . . . . . . . . . . . . . 20
15.2 Wave and reflow soldering . . . . . . . . . . . . . . . 20
15.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 20
15.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 21
16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22
17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
18 Contact information. . . . . . . . . . . . . . . . . . . . . 24
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 August 2010
Document identifier: TJA1054

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TJA1054

Fault-tolerant CAN transceiver

2. Features and benefits

2.1 Optimized for in-car low-speed communication

2.2 Bus failure management

2.4 Support for low power modes

3. Quick reference data

Product data sheet Rev. 4 — 3 August 2010 2 of 25

Fig 1. Block diagram

Product data sheet Rev. 4 — 3 August 2010 3 of 25

ERR 4 TJA1054T 11 CANH

Fig 2. Pin configuration

6.2 Pin description

Product data sheet Rev. 4 — 3 August 2010 4 of 25

7.1 Failure detector

Product data sheet Rev. 4 — 3 August 2010 5 of 25

Table 4. Bus failures

[1] A weak termination implies a pull-down current source behavior of 75 μA typical.

Recovery from failures 3, 3a and 6 is detected automatically after reading a consecutive

Product data sheet Rev. 4 — 3 August 2010 6 of 25

7.2 Low power modes

Table 5. Normal operating and low power modes

Standby LOW LOW

[1] If the supply voltage VCC is present

• The bus lines for remote wake-up

Product data sheet Rev. 4 — 3 August 2010 7 of 25

• VBAT power-on (cold start)

Product data sheet Rev. 4 — 3 August 2010 8 of 25

(1) STANDBY SLEEP

Mode 10 stands for: Pin STB = HIGH and pin EN = LOW.

Product data sheet Rev. 4 — 3 August 2010 9 of 25

Table 6. Limiting values …continued

Product data sheet Rev. 4 — 3 August 2010 10 of 25

10. Static characteristics

Product data sheet Rev. 4 — 3 August 2010 11 of 25

Table 8. Static characteristics …continued

Product data sheet Rev. 4 — 3 August 2010 12 of 25

Table 8. Static characteristics …continued

Product data sheet Rev. 4 — 3 August 2010 13 of 25

Table 8. Static characteristics …continued

11. Dynamic characteristics

Product data sheet Rev. 4 — 3 August 2010 14 of 25

Table 9. Dynamic characteristics …continued

Product data sheet Rev. 4 — 3 August 2010 15 of 25

tPD(L) tPD(H) 015aaa175

Vdiff = VCANH − VCANL

12. Test information

INH BAT VCC

Product data sheet Rev. 4 — 3 August 2010 16 of 25

INH BAT VCC

CTX0 CRXO Px.x Px.x Px.x

TXD RXD STB ERR EN INH

CAN BUS LINE

Fig 7. Application diagram

12.1 Quality information

Product data sheet Rev. 4 — 3 August 2010 17 of 25

13. Bare die information

Fig 8. Bonding pad locations

Product data sheet Rev. 4 — 3 August 2010 18 of 25

14. Package outline