Tja1042 1

TJA1042
High-speed CAN transceiver with Standby mode

Rev. 11 — 16 January 2023 Product data sheet
1 General description
The TJA1042 high-speed CAN transceiver provides an interface between a Controller
Area Network (CAN) protocol controller and the physical two-wire CAN bus. The
transceiver is designed for high-speed CAN applications in the automotive industry,
providing the differential transmit and receive capability to (a microcontroller with) a CAN
protocol controller.
The TJA1042 belongs to the third generation of high-speed CAN transceivers from NXP
Semiconductors, offering significant improvements over first- and second-generation
devices such as the TJA1040. It offers improved ElectroMagnetic Compatibility (EMC)
and ElectroStatic Discharge (ESD) performance, and also features:
• Ideal passive behavior to the CAN bus when the supply voltage is off
• A very low-current Standby mode with bus wake-up capability
• Variants with a VIO pin can be interfaced directly with microcontrollers with supply
voltages from 3.3 V to 5 V
The TJA1042 implements the CAN physical layer as defined in ISO 11898-2:2016 and
SAE J2284-1 to SAE J2284-5. This implementation enables reliable communication
in the CAN FD fast phase at data rates up to 5 Mbit/s. The TJA1042B and TJA1042C
feature shorter propagation delay, supporting larger network topologies.
These features make the TJA1042 an excellent choice for all types of HS-CAN networks,
in nodes that require a low-power mode with wake-up capability via the CAN bus.
2 Features and benefits
2.1 General
• Fully ISO 11898-2:2016, SAE J2284-1 to SAE J2284-5 and SAE J1939-14 compliant
• Timing guaranteed for data rates up to 5 Mbit/s in the CAN FD fast phase
• Suitable for 12 V and 24 V systems
• Low Electromagnetic Emission (EME) and high Electromagnetic Immunity (EMI),
according to proposed EMC Standards IEC 62228-3 and SAE J2962-2
• Variants with a VIO pin allow for direct interfacing with 3.3 V to 5 V microcontrollers
• Shorter propagation delay on the TJA1042B and TJA1042C variants supports larger
network topologies (see Table 8)
• SPLIT voltage output on TJA1042T and TJA1042CT for stabilizing the recessive bus
level
• Both VIO and non-VIO variants are available in SO8 and leadless HVSON8 (3.0 mm
× 3.0 mm) packages; HVSON8 with improved Automated Optical Inspection (AOI)
capability.
NXP Semiconductors
TJA1042
• Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
• AEC-Q100 qualified
2.2 Predictable and fail-safe behavior

• Very low-current Standby mode with host and bus wake-up capability
• Functional behavior predictable under all supply conditions
• Transceiver disengages from the bus (high-ohmic) when the supply voltage drops
below the switch-off undervoltage threshold
• Transmit Data (TXD) dominant time-out function
• Bus-dominant time-out function in Standby mode
• Undervoltage detection on pins VCC and VIO
2.3 Protections
• High ESD handling capability on the bus pins (±8 kV)
• High voltage robustness on CAN pins (±58 V)
• Bus pins protected against transients in automotive environments
• Thermally protected
3 Quick reference data

Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 4.5 - 5.5 V
VIO supply voltage on pin VIO 2.8 - 5.5 V
Vuvd(VCC) undervoltage detection voltage 3.5 - 4.5 V
on pin VCC
Vuvd(VIO) undervoltage detection voltage 1.3 2.0 2.7 V
on pin VIO
ICC supply current Standby mode - 10 15 μA
Normal mode; bus recessive 2.5 5 10 mA
Normal mode; bus dominant 20 45 70 mA
IIO supply current on pin VIO Standby mode; VTXD = VIO 5 - 14 μA
Normal mode
recessive; VTXD = VIO 15 80 200 μA
dominant; VTXD = 0 V - 350 1000 μA
VESD electrostatic discharge voltage IEC 61000-4-2 at pins CANH and CANL -8 - +8 kV
VCANH voltage on pin CANH -58 - +58 V
VCANL voltage on pin CANL -58 - +58 V
Tvj virtual junction temperature -40 - +150 °C
TJA1042 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
Product data sheet Rev. 11 — 16 January 2023

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TJA1042
4 Ordering information
Table 2. Ordering information
[1]
Type number Package
Name Description Version
TJA1042T SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
TJA1042BT
TJA1042CT
TJA1042T/3
TJA1042BTK HVSON8 plastic thermal enhanced very thin small outline package; no leads; SOT782-1
TJA1042TK/3 8 terminals; body 3 × 3 × 0.85 mm
[1] TJA1042T and TJA1042CT with SPLIT pin; other variants with VIO pin.
5 Block diagram
VIO VCC
5 3
VCC TJA1042
TEMPERATURE
PROTECTION
VIO(1) 7
CANH
SLOPE
CONTROL
AND
1 TIME-OUT 6
TXD DRIVER CANL
VIO(1)
MODE 5
8 CONTROL SPLIT SPLIT(1)
STB
4
RXD
MUX
AND
DRIVER
WAKE-UP
FILTER
015aaa017
GND
1. In a transceiver with a SPLIT pin, the VIO input is internally connected to VCC.
Figure 1. Block diagram

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6 Pinning information
6.1 Pinning
TJA1042T TJA1042T/3 TJA1042TK/3

TJA1042CT TJA1042BT terminal 1 TJA1042BTK
index area
TXD 1 8 STB TXD 1 8 STB TXD 1 8 STB
GND 2 7 CANH
GND 2 7 CANH GND 2 7 CANH
VCC 3 6 CANL
VCC 3 6 CANL VCC 3 6 CANL RXD 4 5 VIO
RXD 4 5 SPLIT RXD 4 5 VIO
015aaa239
015aaa018 015aaa019 Transparent top view
SO8 SO8 HVSON8
Figure 2. Pin configuration diagrams
6.2 Pin description

Table 3. Pin description
[1]
Symbol Pin Type Description
TXD 1 I transmit data input
[2]
GND 2 G ground supply
VCC 3 P supply voltage
RXD 4 O receive data output; reads out data from the bus lines
SPLIT 5 O common-mode stabilization output; TJA1042T and
TJA1042CT variants only
VIO 5 P supply voltage for I/O level adapter; TJA1042T(K)/3 and
TJA1042BT(K) variants only
CANL 6 AIO LOW-level CAN bus line
CANH 7 AIO HIGH-level CAN bus line
STB 8 I Standby mode control input
[1] I: digital input; O: digital output; AIO: analog input/output; P: power supply; G: ground.
[2] HVSON8 package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must
be soldered to board ground. For enhanced thermal and electrical performance, it is recommended that the exposed
center pad also be soldered to board ground.

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7 Functional description
The TJA1042 is a HS-CAN stand-alone transceiver with Standby mode. It combines the
functionality of the PCA82C250, PCA82C251 and TJA1040 transceivers with improved
EMC and ESD handling capability and quiescent current performance. Improved slope
control and high DC handling capability on the bus pins provide additional application
flexibility.
The TJA1042 is available in two versions, distinguished only by the function of pin 5:
• The TJA1042T and TJA1042CT are backwards compatible with the TJA1040 when
used with a 5 V microcontroller, and also cover existing PCA82C250 and PCA82C251
applications
• The TJA1042T(K)/3 and TJA1042BT(K) allow for direct interfacing to microcontrollers
with supply voltages down to 3 V
7.1 Operating modes

The TJA1042 supports two operating modes, Normal and Standby, which are selected
via pin STB. See Table 4 for a description of the operating modes under normal supply
conditions.
Table 4. Operating modes

Mode Pin STB Pin RXD
LOW HIGH
Normal LOW bus dominant bus recessive
Standby HIGH wake-up request no wake-up request
detected detected
7.1.1 Normal mode

A LOW level on pin STB selects Normal mode. In this mode, the transceiver can transmit
and receive data via the bus lines CANH and CANL (see Figure 1 for the block diagram).
The differential receiver converts the analog data on the bus lines into digital data which
is output to pin RXD. The slopes of the output signals on the bus lines are controlled
internally and are optimized in a way that guarantees the lowest possible EME.
7.1.2 Standby mode

A HIGH level on pin STB selects Standby mode. In Standby mode, the transceiver is not
able to transmit or correctly receive data via the bus lines. The transmitter and Normal-
mode receiver blocks are switched off to reduce supply current, and only a low-power
differential receiver monitors the bus lines for activity. The wake-up filter on the output
of the low-power receiver does not latch bus dominant states, but ensures that only bus
dominant and bus recessive states that persist longer than tfltr(wake)bus are reflected on pin
RXD.
In Standby mode, the bus lines are biased to ground to minimize the system supply
current. The low-power receiver is supplied by VIO, and is capable of detecting CAN
bus activity even if VIO is the only supply voltage available. When pin RXD goes LOW to
signal a wake-up request, a transition to Normal mode will not be triggered until STB is
forced LOW.

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TJA1042
CANH
VO(dif)
CANL
tfltr(wake)bus tfltr(wake)bus tfltr(wake)bus tfltr(wake)bus

t < tfltr(wake)bus t < tfltr(wake)bus
RXD
aaa-022658
Figure 3. Wake-up timing
7.2 Fail-safe features
7.2.1 TXD dominant time-out function

A ‘TXD dominant time-out’ timer is started when pin TXD is set LOW. If the LOW state on
pin TXD persists for longer than tto(dom)TXD, the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD is set to
HIGH. The TXD dominant time-out time also defines the minimum possible bit rate of
40 kbit/s.
7.2.2 Bus dominant time-out function

In Standby mode a 'bus dominant time-out' timer is started when the CAN bus changes
from recessive to dominant state. If the dominant state on the bus persists for longer
than tto(dom)bus, the RXD pin is reset to HIGH. This function prevents a clamped dominant
bus (due to a bus short-circuit or a failure in one of the other nodes on the network) from
generating a permanent wake-up request. The bus dominant time-out timer is reset when
the CAN bus changes from dominant to recessive state.
7.2.3 Internal biasing of TXD and STB input pins

Pins TXD and STB have internal pull-ups to VIO to ensure a safe, defined state in case
one or both of these pins are left floating. Pull-up currents flow in these pins in all states;
both pins should be held HIGH in Standby mode to minimize standby current.
7.2.4 Undervoltage detection on pins VCC and VIO

Should VCC drop below the VCC undervoltage detection level, Vuvd(VCC), the transceiver
will switch to Standby mode. The logic state of pin STB will be ignored until VCC has
recovered.
Should VIO drop below the VIO undervoltage detection level, Vuvd(VIO), the transceiver will
switch off and disengage from the bus (zero load) until VIO has recovered.

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7.2.5 Overtemperature protection

The output drivers are protected against overtemperature conditions. If the virtual
junction temperature exceeds the shutdown junction temperature, Tj(sd), the output
drivers will be disabled until the virtual junction temperature falls below Tj(sd) and TXD
becomes recessive again. Including the TXD condition ensures that output driver
oscillation due to temperature drift is avoided.
7.3 SPLIT output pin and VIO supply pin

Two versions of the TJA1042 are available, only differing in the function of a single pin.
Pin 5 is either a SPLIT output pin or a VIO supply pin.
7.3.1 SPLIT pin

Using the SPLIT pin on the TJA1042T and TJA1042CT in conjunction with a split
termination network (see Figure 4 and Figure 7) can help to stabilize the recessive
voltage level on the bus. This will reduce EME in networks with DC leakage to ground
(e.g. from deactivated nodes with poor bus leakage performance). In Normal mode, pin
SPLIT delivers a DC output voltage of 0.5VCC. In Standby mode or when VCC is off, pin
SPLIT is floating. When not used, the SPLIT pin should be left open.
VCC
TJA1042T
CANH
R 60 Ω
VSPLIT = 0.5 VCC SPLIT
in normal mode;
otherwise floating
R 60 Ω
CANL
GND 015aaa020
Figure 4. Stabilization circuitry and application for version with SPLIT pin
7.3.2 VIO supply pin

Pin VIO on the TJA1042T(K)/3 and TJA1042BT(K) variants should be connected to the
microcontroller supply voltage (see Figure 8). This will adjust the signal levels of pins
TXD, RXD and STB to the I/O levels of the microcontroller. Pin VIO also provides the
internal supply voltage for the low-power differential receiver of the transceiver. For
applications running in low-power mode, this allows the bus lines to be monitored for
activity even if there is no supply voltage on pin VCC.
For versions of the TJA1042 without a VIO pin, the VIO input is internally connected to
VCC. This sets the signal levels of pins TXD, RXD and STB to levels compatible with 5 V
microcontrollers.

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TJA1042
8 Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134); all voltages are referenced to ground.
Symbol Parameter Conditions Min Max Unit
[1]
Vx voltage on pin x on pins CANH, CANL and SPLIT -58 +58 V
on any other pin -0.3 +7 V
V(CANH-CANL) voltage between pin CANH -27 +27 V
and pin CANL
[2]
Vtrt transient voltage on pins CANH, CANL
pulse 1 -100 - V
pulse 2a - 75 V
pulse 3a -150 - V
pulse 3b - 100 V
[3]
VESD electrostatic discharge voltage IEC 61000-4-2 (150 pF, 330 Ω discharge circuit)
at pins CANH and CANL -8 +8 kV
Human Body Model (HBM)
[4]
on any pin -4 +4 kV
[5]
at pins CANH and CANL -8 +8 kV
[6]
Machine Model (MM); 200 pF, 0.75 μH, 10 Ω
at any pin -300 +300 V
[7]
Charged Device Model (CDM)
at corner pins -750 +750 V
at any pin -500 +500 V
[8]
Tvj virtual junction temperature -40 +150 °C
[9]
Tstg storage temperature -55 +150 °C
[1] The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients) never exceed these
values.
[2] Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO 7637.
[3] Verified by an external test house according to IEC TS 62228, Section 4.3.
[4] According to AEC-Q100-002.
[5] Pins stressed to reference group containing all ground and supply pins, emulating the application circuits (Figure 7 and Figure 8). HBM pulse as specified
in AEC-Q100-002 used.
[8] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P × Rth(vj-a), where Rth(vj-a) is a fixed value to be
used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
[9] Tstg in application according to IEC61360-4. For component transport and storage conditions, see instead IEC61760-2.

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9 Thermal characteristics
Table 6. Thermal characteristics
Value determined for free convection conditions on a JEDEC 2S2P board.
[1]
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient SO8 package; in free air 92 K/W
HVSON8 package; in free air 53 K/W
Rth(j-c) thermal resistance from junction to case HVSON8 package; in free air 14 K/W
Ѱj-top thermal characterization parameter from junction SO8 package; in free air 12 K/W
to top of package
HVSON8 package; in free air 6 K/W
[1] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 μm)
and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 μm).
10 Static characteristics
Table 7. Static characteristics
[1]
Tvj = -40 °C to +150 °C; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V ; RL = 60 Ω; CL = 100 pF unless otherwise specified; all
[2]
voltages are defined with respect to ground; positive currents flow into the IC.
Supply; pin VCC
VCC supply voltage 4.5 - 5.5 V
[3]
Vuvd(VCC) undervoltage detection 3.5 - 4.5 V
voltage on pin VCC
ICC supply current Standby mode
TJA1042(C)T; VTXD = VCC - 10 15 μA
TJA1042T(K)/3, TJA1042BT(K); - - 5 μA
VTXD = VIO
Normal mode
[4]
recessive; VTXD = VIO 2.5 5 10 mA
dominant; VTXD = 0 V 20 45 70 mA
dominant; VTXD = 0 V; 2.5 80 110 mA
short circuit on bus lines;
-3 V < (VCANH = VCANL) < +18 V
[1]
I/O level adapter supply; pin VIO
VIO supply voltage on pin VIO 2.8 - 5.5 V
[3]
Vuvd(VIO) undervoltage detection 1.3 2.0 2.7 V
voltage on pin VIO
IIO supply current on pin VIO Standby mode; VTXD = VIO 5 - 14 μA
Normal mode
recessive; VTXD = VIO 15 80 200 μA
dominant; VTXD = 0 V - 350 1000 μA

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Table 7. Static characteristics...continued

[1]
[2]
Standby mode control input; pin STB
[5] [4] [4]
VIH HIGH-level input voltage 0.7VIO - VIO + V
0.3
[4]
VIL LOW-level input voltage -0.3 - 0.3VIO V
[4]
IIH HIGH-level input current VSTB = VIO -1 - +1 μA
IIL LOW-level input current VSTB = 0 V -15 - -1 μA
CAN transmit data input; pin TXD
[5] [4] [4]
VIH HIGH-level input voltage 0.7VIO - VIO + V
0.3
[4]
VIL LOW-level input voltage -0.3 - 0.3VIO V
[4]
IIH HIGH-level input current VTXD = VIO -5 - +5 μA
IIL LOW-level input current VTXD = 0 V -260 -150 -30 μA
[6]
Ci input capacitance - 5 10 pF
CAN receive data output; pin RXD
[4]
IOH HIGH-level output current VRXD = VIO - 0.4 V -9 -3 -1 mA
IOL LOW-level output current VRXD = 0.4 V; bus dominant 2 5 12 mA
Bus lines; pins CANH and CANL
VO(dom) dominant output voltage VTXD = 0 V; t < tto(dom)TXD
pin CANH; RL = 50 Ω to 65 Ω 2.75 3.5 4.5 V
pin CANL; RL = 50 Ω to 65 Ω 0.5 1.5 2.25 V
Vdom(TX)sym transmitter dominant voltage Vdom(TX)sym = VCC - VCANH - VCANL -400 - +400 mV
symmetry
[6]
VTXsym transmitter voltage symmetry VTXsym = VCANH + VCANL; fTXD = 250 0.9VCC - 1.1VCC V
kHz, 1 MHz and 2.5 MHz; CSPLIT = 4.7 [7]
nF; VCC = 4.75 V to 5.25 V

VO(dif) differential output voltage dominant: Normal mode; VTXD = 0 V; t <
tto(dom)TXD; VCC = 4.75 V to 5.25 V
RL = 45 Ω to 65 Ω 1.5 - 3 V
RL = 45 Ω to 70 Ω 1.5 - 3.3 V
RL = 2 240 Ω 1.5 - 5 V
recessive; no load
[4]
Normal mode: VTXD = VIO -50 - +50 mV
Standby mode -0.2 - +0.2 V
[4]
VO(rec) recessive output voltage Normal mode; VTXD = VIO ; no load 2 0.5VCC 3 V
Standby mode; no load -0.1 - +0.1 V

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[1]
[2]
Vth(RX)dif differential receiver threshold -30 V ≤ VCANL ≤ +30 V;
voltage -30 V ≤ VCANH ≤ +30 V
Normal mode 0.5 0.7 0.9 V
[8]
Standby mode 0.4 0.7 1.15 V
[6]
Vrec(RX) receiver recessive voltage -30 V ≤ VCANL ≤ +30 V;
-30 V ≤ VCANH ≤ +30 V
Normal mode -4 - 0.5 V
Standby mode -4 - 0.4 V
[6]
Vdom(RX) receiver dominant voltage -30 V ≤ VCANL ≤ +30 V;
-30 V ≤ VCANH ≤ +30 V
Normal mode 0.9 - 9.0 V
Standby mode 1.15 - 9.0 V
Vhys(RX)dif differential receiver hysteresis -30 V ≤ VCANL ≤ +30 V; 50 120 200 mV
voltage -30 V ≤ VCANH ≤ +30 V
IO(sc)dom dominant short-circuit output VTXD = 0 V; t < tto(dom)TXD; VCC = 5 V
current
pin CANH; VCANH = -15 V to +40 V -100 -70 - mA
pin CANL; VCANL = -15 V to +40 V - 70 100 mA
[4]
IO(sc)rec recessive short-circuit output Normal mode; VTXD = VIO VCANH = -5 - +5 mA
current VCANL = -27 V to +32 V
IL leakage current VCC = VIO = 0 V or VCC = VIO = shorted -5 - +5 μA
to ground via 47 kΩ; VCANH = VCANL = 5
V
[6]
Ri input resistance -2 V ≤ VCANL ≤ +7 V; 9 15 28 kΩ
-2 V ≤ VCANH ≤ +7 V
[6]
ΔRi input resistance deviation 0 V ≤ VCANL ≤ +5 V; -1 - +1 %
0 V ≤ VCANH ≤ +5 V
[6]
Ri(dif) differential input resistance -2 V ≤ VCANL ≤ +7 V; 19 30 52 kΩ
-2 V ≤ VCANH ≤ +7 V
[6]
Ci(cm) common-mode input - - 20 pF
capacitance
[6]
Ci(dif) differential input capacitance - - 10 pF
Common mode stabilization output; pin SPLIT; only for TJA1042T and TJA1042CT
VO output voltage Normal mode ISPLIT = -500 μA to +500 0.3VCC 0.5VCC 0.7VCC V
μA
Normal mode; RL = 1 MΩ 0.45VCC 0.5VCC 0.55VCC V
IL leakage current Standby mode -5 - +5 μA
VSPLIT = -58 V to +58 V

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[1]
[2]
Temperature detection
[6]
Tj(sd) shutdown junction - 190 - °C
temperature
[1] Only the TJA1042T(K)/3 and TJA1042BT(K) variants have a VIO pin; for the TJA1042T and TJA1042CT variants, the VIO input is internally connected to
VCC.
[2] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified
temperature and power supply voltage range.
[3] Undervoltage is detected between min and max values. Undervoltage is guaranteed to be detected below min value and guaranteed not to be detected
above max value.
[4] VIO = VCC for the non-VIO product variants.
[5] Maximum value assumes VCC < VIO; if VCC > VIO, the maximum value will be VCC + 0.3 V.
[6] Not tested in production; guaranteed by design.
[7] The test circuit used to measure the bus output voltage symmetry (which includes CSPLIT) is shown in Figure 10.
[8] Variants with a a VIO pin: values valid when -12 V ≤ VCANL ≤ +12 V and -12 V ≤ VCANH ≤ +12 V.

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11 Dynamic characteristics
Table 8. Dynamic characteristics
[1]
Tvj = -40 °C to +150 °C; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V ; RL = 60 Ω unless specified otherwise; all voltages are
[2]
defined with respect to ground.
Transceiver timing; pins CANH, CANL, TXD and RXD; seeFigure 5, Figure 6 and Figure 9
td(TXD-busdom) delay time from TXD to bus dominant TJA1042B/C; Normal mode - 60 100 ns
TJA1042T, T(K)/3 - 65 100 ns
td(TXD-busrec) delay time from TXD to bus recessive TJA1042B/C; Normal mode - 70 115 ns
TJA1042T, T(K)/3 - 90 125 ns
td(busdom-RXD) delay time from bus dominant to RXD TJA1042B/C; Normal mode - 55 100 ns
TJA1042T, T(K)/3 - 60 110 ns
td(busrec-RXD) delay time from bus recessive to RXD TJA1042B/C; Normal mode - 60 145 ns
TJA1042T, T(K)/3 - 65 155 ns
td(TXDL-RXDL) delay time from TXD LOW to RXD TJA1042B; Normal mode 60 - 225 ns
LOW
TJA1042C; Normal mode 60 - 195 ns
TJA1042T(K)/3; Normal mode 60 - 250 ns
TJA1042T; Normal mode 60 - 220 ns
td(TXDH-RXDH) delay time from TXD HIGH to RXD TJA1042B; Normal mode 60 - 225 ns
HIGH
TJA1042C; Normal mode 60 - 195 ns
TJA1042T(K)/3; Normal mode 60 - 250 ns
TJA1042T; Normal mode 60 - 220 ns
[3]
tbit(bus) transmitted recessive bit width tbit(TXD) = 500 ns 435 - 530 ns
[3]
tbit(TXD) = 200 ns 155 - 210 ns
[3]
tbit(RXD) bit time on pin RXD tbit(TXD) = 500 ns 400 - 550 ns
[3]
tbit(TXD) = 200 ns 120 - 220 ns
Δtrec receiver timing symmetry tbit(TXD) = 500 ns -65 - +40 ns
tbit(TXD) = 200 ns -45 - +15 ns
[4]
tto(dom)TXD TXD dominant time-out time VTXD = 0 V; Normal mode 0.3 2 5 ms
[5]
tto(dom)bus bus dominant time-out time Standby mode 0.3 2 5 ms
tfltr(wake)bus bus wake-up filter time version with SPLIT pin; Standby mode 0.5 1 3 μs
versions with VIO pin; Standby mode 0.5 1.5 5 μs
td(stb-norm) standby to normal mode delay time 7 25 47 μs
[1] Only the TJA1042T(K)/3 and TJA1042BT(K) variants have a VIO pin; for the TJA1042T and TJA1042CT variants, the VIO input is internally connected to
VCC.
[2] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified
temperature and power supply voltage range.
[3] See Figure 6.
[4] Minimum value of 0.8 ms required according to SAE J2284; 0.3 ms is allowed according to ISO11898-2:2016 for legacy devices. Time-out occurs between
the min and max values. Time-out is guaranteed not to occur below the min value; time-out is guaranteed to occur above the max value.
[5] Time-out occurs between the min and max values. Time-out is guaranteed not to occur below the min value; time-out is guaranteed to occur above the
max value.

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TJA1042
HIGH
70 %
TXD
30 %
LOW
CANH
CANL
dominant
0.9 V
VO(dif)
0.5 V
recessive
HIGH
70 %
RXD
30 %
LOW
td(TXD-busdom) td(TXD-busrec)
td(busdom-RXD) td(busrec-RXD)
aaa-029311
Figure 5. CAN transceiver timing diagram
70 %
TXD
30 % 30 %
5 x tbit(TXD) td(TXDL-RXDL)
tbit(TXD)
VO(dif) 0.9 V
0.5 V
tbit(bus)
70 %
RXD
30 %
td(TXDH-RXDH)
tbit(RXD)
aaa-029312
Figure 6. CAN FD timing definitions according to ISO 11898-2:2016

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NXP Semiconductors
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12 Application information
The minimum external circuitry needed with the TJA1042 is shown in Figure 7 and
Figure 8. See the Application Hints (Section 12.2) for further information about external
components and PCB layout requirements.
12.1 Application diagrams
BAT 5V
(1)
VCC
CANH VDD
CANH Pxx
(2) STB
SPLIT TJA1042T Pyy MICRO-
TJA1042CT TXD CONTROLLER
TX0
CANL RXD
CANL RX0
GND
GND
015aaa022
1. Optional, depends on regulator.

2. Optional common mode stabilization by a voltage source of VCC/2 at pin SPLIT.
Figure 7. Typical TJA1042 application with a 5 V microcontroller (non-VIO variants)
BAT 3.3 V (1)
on/off control
5V
(1)
VCC VIO
CANH VDD
CANH Pxx
STB
Pyy
TJA1042T(K)/3 MICRO-
TJA1042BT(K) TXD CONTROLLER
TX0
CANL RXD
CANL RX0
GND
GND
015aaa021
1. Optional, depends on regulator.

Figure 8. Typical TJA1042 application with a 3.3 V microcontroller (VIO variants).
12.2 Application hints

Further information on the application of the TJA1042 can be found in NXP application
hints AH1014 ‘Application Hints - Standalone high speed CAN transceiver TJA1042/
TJA1043/TJA1048/TJA1051’.

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NXP Semiconductors
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13 Test information
TXD CANH
RL CL
60 Ω 100 pF
RXD CANL
15 pF
aaa-030850
Figure 9. CAN transceiver timing test circuit
TXD CANH
30 Ω
fTXD
CSPLIT
4.7 nF
30 Ω
RXD CANL
aaa-030851
Figure 10. Test circuit for measuring transceiver driver symmetry
13.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.

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NXP Semiconductors
TJA1042
14 Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D E A
X
y HE v M A
8 5
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 4 L
e w M detail X
bp
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
0.25 1.45 0.49 0.25 5.0 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1
0.10 1.25 0.36 0.19 4.8 3.8 5.8 0.4 0.6 0.3 8
o
o
0.010 0.057 0.019 0.0100 0.20 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.19 0.15 0.228 0.016 0.024 0.012
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
99-12-27
SOT96-1 076E03 MS-012
03-02-18
Figure 11. Package outline SOT96-1 (SO8)

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NXP Semiconductors
TJA1042
HVSON8: plastic thermal enhanced very thin small outline package; no leads;
8 terminals; body 3 x 3 x 0.85 mm SOT782-1
D B A
E A
A1
c
detail X
terminal 1
index area
e1
terminal 1 C
index area v C A B
e b
w C y1 C y
1 4
L
K
Eh
8 5
Dh
0 1 2 mm
Dimensions scale
Unit(1) A A1 b c D Dh E Eh e e1 K L v w y y1
max 1.00 0.05 0.35 3.10 2.45 3.10 1.65 0.35 0.45
mm nom 0.85 0.03 0.30 0.2 3.00 2.40 3.00 1.60 0.65 1.95 0.30 0.40 0.1 0.05 0.05 0.1
min 0.80 0.00 0.25 2.90 2.35 2.90 1.55 0.25 0.35
Note
1. Plastic or metal protrusions of 0.075 maximum per side are not included. sot782-1_po
Outline References European

Issue date
version IEC JEDEC JEITA projection
09-08-25
SOT782-1 --- MO-229 ---
09-08-28
Figure 12. Package outline SOT782-1 (HVSON8)

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NXP Semiconductors
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15 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
16 Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
16.3 Wave soldering

Key characteristics in wave soldering are:

19 / 27
NXP Semiconductors
TJA1042
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering

Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 13) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with Table 9
and Table 10
Table 9. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (°C)
Volume (mm³)
< 350 ≥ 350
< 2.5 235 220
≥ 2.5 220 220
Table 10. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (°C)
Volume (mm³)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 13.

20 / 27
NXP Semiconductors
TJA1042
maximum peak temperature

temperature = MSL limit, damage level
minimum peak temperature

= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level

Figure 13. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

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NXP Semiconductors
TJA1042
17 Appendix: ISO 11898-2:2016 parameter cross-reference list

Table 11. ISO 11898-2:2016 to NXP data sheet parameter conversion
ISO 11898-2:2016 NXP data sheet
Parameter Notation Symbol Parameter
HS-PMA dominant output characteristics
Single ended voltage on CAN_H VCAN_H VO(dom) dominant output voltage
Single ended voltage on CAN_L VCAN_L
Differential voltage on normal bus load VDiff VO(dif) differential output voltage
Differential voltage on effective resistance during arbitration
Optional: Differential voltage on extended bus load range
HS-PMA driver symmetry
Driver symmetry VSYM VTXsym transmitter voltage symmetry
Maximum HS-PMA driver output current
Absolute current on CAN_H ICAN_H IO(sc)dom dominant short-circuit output
current
Absolute current on CAN_L ICAN_L
HS-PMA recessive output characteristics, bus biasing active/inactive
Single ended output voltage on CAN_H VCAN_H VO(rec) recessive output voltage
Single ended output voltage on CAN_L VCAN_L
Differential output voltage VDiff VO(dif) differential output voltage
Optional HS-PMA transmit dominant timeout
Transmit dominant timeout, long tdom tto(dom)TXD TXD dominant time-out time
Transmit dominant timeout, short
HS-PMA static receiver input characteristics, bus biasing active/inactive
Recessive state differential input voltage range VDiff Vth(RX)dif differential receiver threshold
Dominant state differential input voltage range voltage
Vrec(RX) receiver recessive voltage
Vdom(RX) receiver dominant voltage
HS-PMA receiver input resistance (matching)
Differential internal resistance RDiff Ri(dif) differential input resistance
Single ended internal resistance RCAN_H Ri input resistance
RCAN_L
Matching of internal resistance MR ΔRi input resistance deviation
HS-PMA implementation loop delay requirement
Loop delay tLoop td(TXDH-RXDH) delay time from TXD HIGH to
RXD HIGH
td(TXDL-RXDL) delay time from TXD LOW to
RXD LOW

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NXP Semiconductors
TJA1042
Table 11. ISO 11898-2:2016 to NXP data sheet parameter conversion...continued

ISO 11898-2:2016 NXP data sheet
Parameter Notation Symbol Parameter
Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to 2
Mbit/s and above 2 Mbit/s up to 5 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s, tBit(Bus) tbit(bus) transmitted recessive bit width
intended
Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s tBit(RXD) tbit(RXD) bit time on pin RXD
Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s ΔtRec Δtrec receiver timing symmetry
HS-PMA maximum ratings of VCAN_H, VCAN_L and VDiff
Maximum rating VDiff VDiff V(CANH-CANL) voltage between pin CANH and
pin CANL
General maximum rating VCAN_H and VCAN_L VCAN_H Vx voltage on pin x
Optional: Extended maximum rating VCAN_H and VCAN_L VCAN_L
HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered
Leakage current on CAN_H, CAN_L ICAN_H IL leakage current
ICAN_L
HS-PMA bus biasing control timings
[1]
CAN activity filter time, long tFilter twake(busdom) bus dominant wake-up time
[1]
CAN activity filter time, short twake(busrec) bus recessive wake-up time
Wake-up timeout, short tWake tto(wake)bus bus wake-up time-out time
Wake-up timeout, long
Timeout for bus inactivity tSilence tto(silence) bus silence time-out time
Bus Bias reaction time tBias td(busact-bias) delay time from bus active to bias
[1] tfltr(wake)bus - bus wake-up filter time, in devices with basic wake-up functionality

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NXP Semiconductors
TJA1042
18 Revision history
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TJA1042 v.11 20230116 Product data sheet - TJA1042 v.10
Modifications: • Added variants TJA1042BT(K) and TJA1042CT with shorter propagation delay
• Section 2.1: SAE J1939-14 compliance added
• Section 2.1: EMC compliance updated to latest standards IEC 62228-3 and SAE J2962-2
• Section 2.2: updated text describing supply undervoltage behavior
• Table 3: pin type column added
• Table 5: format and footnotes revised; no specification changes
• Table 6: parameter definitions and specifications updated
• Table 7: footnotes updated/added; parameter values changed: IO(sc)dom, IOH for pin RXD (min value)
• Table 8: delay time parameter values revised and footnotes updated/added
• Figure 5 and Figure 6: timing diagrams revised
• Section 12: introductory paragraph added
• Figure 9 and Figure 10: drawings revised
• Section 17: 'Soldering of HVSON packages' removed
• Section 19: legal information updated
TJA1042 v.1 20090309 Product data sheet - -

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NXP Semiconductors
TJA1042
19 Legal information
19.1 Data sheet status

[1][2] [3]
Document status Product status Definition
Objective [short] data sheet Development This document contains data from the objective specification for product
development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
Draft — A draft status on a document indicates that the content is still specified use without further testing or modification.
under internal review and subject to formal approval, which may result
Customers are responsible for the design and operation of their
in modifications or additions. NXP Semiconductors does not give any
applications and products using NXP Semiconductors products, and NXP
representations or warranties as to the accuracy or completeness of
Semiconductors accepts no liability for any assistance with applications or
information included in a draft version of a document and shall have no
customer product design. It is customer’s sole responsibility to determine
liability for the consequences of use of such information.
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
Short data sheet — A short data sheet is an extract from a full data sheet application and use of customer’s third party customer(s). Customers should
with the same product type number(s) and title. A short data sheet is provide appropriate design and operating safeguards to minimize the risks
intended for quick reference only and should not be relied upon to contain associated with their applications and products.
detailed and full information. For detailed and full information see the
NXP Semiconductors does not accept any liability related to any default,
relevant full data sheet, which is available on request via the local NXP
damage, costs or problem which is based on any weakness or default
Semiconductors sales office. In case of any inconsistency or conflict with the
in the customer’s applications or products, or the application or use by
short data sheet, the full data sheet shall prevail.
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Product specification — The information and data provided in a Product
Semiconductors products in order to avoid a default of the applications
data sheet shall define the specification of the product as agreed between
and the products or of the application or use by customer’s third party
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer(s). NXP does not accept any liability in this respect.
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
Limiting values — Stress above one or more limiting values (as defined in
is deemed to offer functions and qualities beyond those described in the
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
Product data sheet.
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
19.3 Disclaimers Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
Limited warranty and liability — Information in this document is believed the quality and reliability of the device.
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy Terms and conditions of commercial sale — NXP Semiconductors
or completeness of such information and shall have no liability for the products are sold subject to the general terms and conditions of commercial
consequences of use of such information. NXP Semiconductors takes no sale, as published at http://www.nxp.com/profile/terms, unless otherwise
responsibility for the content in this document if provided by an information agreed in a valid written individual agreement. In case an individual
source outside of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective
In no event shall NXP Semiconductors be liable for any indirect, incidental, agreement shall apply. NXP Semiconductors hereby expressly objects to
punitive, special or consequential damages (including - without limitation - applying the customer’s general terms and conditions with regard to the
lost profits, lost savings, business interruption, costs related to the removal purchase of NXP Semiconductors products by customer.
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of No offer to sell or license — Nothing in this document may be interpreted
contract or any other legal theory. or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
Notwithstanding any damages that customer might incur for any reason
patents or other industrial or intellectual property rights.
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited in
accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

25 / 27
NXP Semiconductors
TJA1042
Suitability for use in automotive applications — This NXP product has Security — Customer understands that all NXP products may be subject to
been qualified for use in automotive applications. If this product is used unidentified vulnerabilities or may support established security standards or
by customer in the development of, or for incorporation into, products or specifications with known limitations. Customer is responsible for the design
services (a) used in safety critical applications or (b) in which failure could and operation of its applications and products throughout their lifecycles
lead to death, personal injury, or severe physical or environmental damage to reduce the effect of these vulnerabilities on customer’s applications
(such products and services hereinafter referred to as “Critical Applications”), and products. Customer’s responsibility also extends to other open and/or
then customer makes the ultimate design decisions regarding its products proprietary technologies supported by NXP products for use in customer’s
and is solely responsible for compliance with all legal, regulatory, safety, applications. NXP accepts no liability for any vulnerability. Customer should
and security related requirements concerning its products, regardless of regularly check security updates from NXP and follow up appropriately.
any information or support that may be provided by NXP. As such, customer Customer shall select products with security features that best meet rules,
assumes all risk related to use of any products in Critical Applications and regulations, and standards of the intended application and make the
NXP and its suppliers shall not be liable for any such use by customer. ultimate design decisions regarding its products and is solely responsible
Accordingly, customer will indemnify and hold NXP harmless from any for compliance with all legal, regulatory, and security related requirements
claims, liabilities, damages and associated costs and expenses (including concerning its products, regardless of any information or support that may be
attorneys’ fees) that NXP may incur related to customer’s incorporation of provided by NXP.
any product in a Critical Application. NXP has a Product Security Incident Response Team (PSIRT) (reachable
at PSIRT@nxp.com) that manages the investigation, reporting, and solution
Quick reference data — The Quick reference data is an extract of the release to security vulnerabilities of NXP products.
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein 19.4 Trademarks
may be subject to export control regulations. Export might require a prior
authorization from competent authorities. Notice: All referenced brands, product names, service names, and
trademarks are the property of their respective owners.
Translations — A non-English (translated) version of a document, including
NXP — wordmark and logo are trademarks of NXP B.V.
the legal information in that document, is for reference only. The English
version shall prevail in case of any discrepancy between the translated and
English versions.

26 / 27
NXP Semiconductors
TJA1042
Contents
1 General description ............................................ 1
2 Features and benefits .........................................1
2.1 General .............................................................. 1
2.2 Predictable and fail-safe behavior ..................... 2
2.3 Protections ......................................................... 2
3 Quick reference data .......................................... 2
4 Ordering information .......................................... 3
5 Block diagram ..................................................... 3
6 Pinning information ............................................ 4
6.1 Pinning ............................................................... 4
6.2 Pin description ................................................... 4
7 Functional description ........................................5
7.1 Operating modes ............................................... 5
7.1.1 Normal mode ..................................................... 5
7.1.2 Standby mode ................................................... 5
7.2 Fail-safe features ............................................... 6
7.2.1 TXD dominant time-out function ........................ 6
7.2.2 Bus dominant time-out function ......................... 6
7.2.3 Internal biasing of TXD and STB input pins ....... 6
7.2.4 Undervoltage detection on pins VCC and
VIO .....................................................................6
7.2.5 Overtemperature protection ............................... 7
7.3 SPLIT output pin and VIO supply pin ................ 7
7.3.1 SPLIT pin ...........................................................7
7.3.2 VIO supply pin ................................................... 7
8 Limiting values .................................................... 8
9 Thermal characteristics ......................................9
10 Static characteristics .......................................... 9
11 Dynamic characteristics ...................................13
12 Application information .................................... 15
12.1 Application diagrams ....................................... 15
12.2 Application hints .............................................. 15
13 Test information ................................................ 16
13.1 Quality information ...........................................16
14 Package outline .................................................17
15 Handling information ........................................ 19
16 Soldering of SMD packages .............................19
16.1 Introduction to soldering .............................
16.2 Wave and reflow soldering .........................
16.3 Wave soldering ...........................................
16.4 Reflow soldering .........................................
17 Appendix: ISO 11898-2:2016 parameter
cross-reference list ........................................... 22
18 Revision history ................................................ 24
19 Legal information .............................................. 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© 2023 NXP B.V. All rights reserved.

For more information, please visit: http://www.nxp.com
Date of release: 16 January 2023
Document identifier: TJA1042

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TJA1042

High-speed CAN transceiver with Standby mode

2 Features and benefits

2.2 Predictable and fail-safe behavior

3 Quick reference data

Product data sheet Rev. 11 — 16 January 2023

Product data sheet Rev. 11 — 16 January 2023

TJA1042T TJA1042T/3 TJA1042TK/3

SO8 SO8 HVSON8

Figure 2. Pin configuration diagrams

6.2 Pin description

Product data sheet Rev. 11 — 16 January 2023

7.1 Operating modes

Table 4. Operating modes

7.1.1 Normal mode

7.1.2 Standby mode

Product data sheet Rev. 11 — 16 January 2023

tfltr(wake)bus tfltr(wake)bus tfltr(wake)bus tfltr(wake)bus

Figure 3. Wake-up timing

7.2 Fail-safe features

7.2.1 TXD dominant time-out function

7.2.2 Bus dominant time-out function

7.2.3 Internal biasing of TXD and STB input pins

7.2.4 Undervoltage detection on pins VCC and VIO

Product data sheet Rev. 11 — 16 January 2023

7.2.5 Overtemperature protection

7.3 SPLIT output pin and VIO supply pin

7.3.1 SPLIT pin

7.3.2 VIO supply pin

Product data sheet Rev. 11 — 16 January 2023

Product data sheet Rev. 11 — 16 January 2023

Product data sheet Rev. 11 — 16 January 2023

Table 7. Static characteristics...continued

nF; VCC = 4.75 V to 5.25 V

Product data sheet Rev. 11 — 16 January 2023

Table 7. Static characteristics...continued

Product data sheet Rev. 11 — 16 January 2023

Table 7. Static characteristics...continued

Product data sheet Rev. 11 — 16 January 2023

Product data sheet Rev. 11 — 16 January 2023

Figure 5. CAN transceiver timing diagram

Figure 6. CAN FD timing definitions according to ISO 11898-2:2016

Product data sheet Rev. 11 — 16 January 2023

12.1 Application diagrams

1. Optional, depends on regulator.

BAT 3.3 V (1)

1. Optional, depends on regulator.

12.2 Application hints

Product data sheet Rev. 11 — 16 January 2023

Figure 9. CAN transceiver timing test circuit

Figure 10. Test circuit for measuring transceiver driver symmetry

13.1 Quality information

Product data sheet Rev. 11 — 16 January 2023

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

OUTLINE REFERENCES EUROPEAN

Figure 11. Package outline SOT96-1 (SO8)

Product data sheet Rev. 11 — 16 January 2023

Outline References European

Figure 12. Package outline SOT782-1 (HVSON8)