Physical Properties of Gates: o Objectives o Reading Assignment

3.
Physical Properties of Gates

o Objectives o Reading Assignment
u Chapter 3 in Brown and Vranesic except the material on
This section discusses some of the physical characteristics of programmable logic devices (sections 3.6, 3.7 and 3.10).
integrated circuits. It will: u Notes=>Supplemental Notes=>Gates (On the 326 web page)
n Develop a very simple structural model for gates that
u Notes=>Supplemental Notes=>Review of Electric Circuits (on the
demonstrates how they work. 326 web page)
n Review the structure of MOS gates.
n Discuss some of the differenced between real and ideal
gates.
n Discuss some of the physical properties of gates.
u Timing, voltage and current properties
n Introduce some special types of gate inputs and outputs.
u Tri-state and open collector outputs and Schmidt trigger inputs.
Elec 326 3.1 Physical Properties of Gates Elec 326 3.2 Physical Properties of Gates
3.1. A Structural Model for Gates

This section presents a very simple structural model n Switch States:
of gates based on an idealized device called a Logic u Closed: Switch conducts between its data terminals.
Switch. u Open: No conduction between the data terminals.
u When C=0, the switch is in its normal state.
o Logic Switches u When C=1, the switch is in its active or on state.
u When C=1, the arm is pulled towards the C input.
n Definition: A Logic Switch is a three-terminal device that
is used to control the connection of two points in a circuit. n Ideal Switch Assumption:
u 0 resistance when closed, • resistance when open.
Data Data u 0 delay switching between open and closed.
Terminal Terminal
Control Control
n Real electronic switches are implemented with transistors,
Terminal C Terminal C and they fail to meet the ideal switch assumptions in that:
Data Data
Terminal Terminal u Resistance in open state is high, but not infinite.
Normally Open Switch Normally Closed Switch u Resistance in closed state is low, but not zero.
u Time required to change states is greater than zero.
1
o Switch Implementations of Gates
o Exercise: n Inverters +
The following switch network conducts between its two +
terminals just in case both the signals X and Y are 1.

Y X Y
X X
Y Passive Pullup Active Pullup
n NAND Gates +
Design three two-terminal networks, each with two control
signals X and Y, such that the networks conduct just in +
case:
Z Z
u Network 1: X is 1 or Y is 1.
X X
u Network 2: X is 1 and Y is 0.
u Network 3: X and Y are equal Y Y
Passive Pullup Active Pullup
n NOR Gates n General Model

+ u Passive pullup
Z Z
X
Z = 01 if T conducts
if T open
X
X0
Y Y
X1
T
Xn
Passive Pullup Active Pullup
Passive Pullup
2
u Active pullup n Comments on the previous diagrams:
u The boxes labeled T and T' contain switches connected in such a
way that they establish a connection between the top and bottom
Note: T' is the complement of T,
so that T' conducts if and only if terminals when the input signals take on certain values and cause
T' T does not conduct an open circuit if the input signals take on any other values.
u The two networks in the active pullup circuit must be be designed
0 if T conducts & T' open so that they are never both conducting or are both open at the same
Z=
1 if T' conducts & T open time.
X0
X1 u For the inverter, T connects the terminals iff the input X is 1.
T
Xn u For the NAND gates T connects iff both X and Y are 1.
u For the NOR gate T connects iff either X or Y is 1.

Active Pullup
3.2. MOSFET Transistors

o N-Channel MOSFET Transistors
o Metal-Oxide-Semiconductor Field Effect Transistors
(MOSFETs) are the transistors most widely used in
integrated circuits today
n The name is due to:
u The structure of the device - a sandwich of a metal conductor, an
oxide insulator, and a semiconductor substrate) and
Source Drain
u The way it works - an electric field controls the flow of current
through the device Equivalent Circuit for Cutoff
MOSFET
n Although early MOSFET transistors used metal for the first
layer, current ones use a polysilicon material (a conductor
with somewhat more resistance than a conductor), which is
easier to fabricate
n With no voltage between the gate terminal and the substrate, there are
two junctions between the two N regions and the P region.
u This acts like two oppositely connected diodes, and no current can flow
between source and drain.
3
o P-Channel MOSFIT Transistors
Gate
Terminal
Gate
Drain
Source
Terminal Terminal
Oxide
Insulator
P N P
Source Drain
Substrate
P-Channel MOSFET
n Application of a positive voltage between the gate terminal
and the substrate creates an electric field that drives holes n The P and N regions are reversed from the N-Channel device.
out of the region under the gate, creating a channel of N- n Application of a voltage on the gate terminal that is negative relative to
type material that connects the source and drain terminals the substrate creates a P channel beneath the gate and charge flow is
u Current is due to electron movement due to hole movement.
o Complementary MOSFETS (CMOS) n The following symbols are used to represent MOSFET
transistors in circuit diagrams:
n N-Channel and P-Channel transistors can be fabricated on
the same substrate as shown below Drain
Terminal
Drain
Terminal
Gate Gate
Terminal Terminal
Source Source
Terminal Terminal
N-Channel P-Channel
MOSFET Symbol MOSFET Symbol
u The ideal normally closed switches presented in Section 4.1 are

models for the MOSFET transistors
Data Data
Terminal Terminal
Control Control
Terminal C Terminal C
Data Data
Terminal Terminal
Normally Open Switch Normally Closed Switch
4
3.3. NMOS and CMOS Logic Families
VDD
VDD
Z
X
Z
X Y
NMOS Inverter
CMOS NOR Gate
3.4. TTL Logic Families

o Properties of NMOS and CMOS gates
n No current flows through the gate unless the input signal is o Basic TTL NAND Gate
5v
changing
u High input impedance
vo
u High fanout T1
vi T2
n Sandwich structure of MOS transistor creates capacitor vi
2
1
between the gate and substrate vi

3
u High input capacitance o TTL gate with Totem Pole Output
u Slows transition time
u Limits fan-out or switching speed
n NMOS dissipates power in low output state
n CMOS gate only dissipates power when it is changing state
u The faster a CMOS gate switches the more power it dissipates, so
there is a tradeoff between speed and power
5
o TTL Families o Packaging of TTL integrated circuits
n Dual in line packages
Series Delay Power Speed-Power

74Hxx 6ns 22mW 132pJ
74xx 10ns 10mW 100pJ pin 1 pin 28
74Sxx 3ns 19mW 57pJ pin 1
pin 20
74Lxx 33ns 1mW 33pJ pin 1 pin 14

74LSxx 9.5ns 2mW 19pJ
74ASxx 1.5ns 10mW 15pJ
74ALSxx 4ns 1mW 4pJ pin 11
pin 8
pin 15
3.5. Differences Between Real and Ideal Gates

7400 7404 7411 7420
1 VCC 14 1 VCC 14 1 VCC 14 1 VCC 14

o Some of the most important differences between real
2 13 2 13 2 13 2 13
and ideal gates are due to the resistance of the real
3 12 3 12 3 12 3 12
switches
4 11 4 11 4 11 4 11
n As indicated previously, a transistor switch has a small, but
5 10 5 10 5 10 5 10
non-zero, resistance in the on state and a large, but not
6 9 6 9 6 9 6 9
infinite, in the off state.
7 GND 8 7 GND 8 7 GND 8 7 GND 8
n This resistance has two major effects:
u The output voltages of the gates are adversely affected.
n The number of gates per SSI and MSI chip is limited by the number of u The gates require non-zero time to switch states.
pins on the chip, not the physical size of the gates.
n All chips must be connected to a power source (VCC) and ground
(GND). All the gates in the chip share these connections.
6
o Effects of capacitance on gate speed
o Effect of Switch Resistance on Output Voltage
n There is internal capacitance associated with transistor
n A grossly simplified model of a gate that shows the effect junctions and wires inside the gate, over which the logic
of switch resistance is as follows
designer has little or no control.
u Charging and discharging this capacitance results in delay between
input and output signal changes.
n There is external capacitance due to external wires (stray
capacitance) and input capacitance associated with gate
input terminals.
u Charging and discharging this capacitance results in slow rise and
Vo = fall times of signals.
u In the low state the output voltage of an ideal gate is 0 since R 2 is 0. n Therefore a better (but still grossly simplified) electrical
In a real gate, the output voltage equals the voltage drop across R 2, model of the gate on the left is given on the right.
which will be greater than 0.
u In the high state the output voltage of an ideal gate will be V since
R1 is 0. In a real gate, the output voltage is V minus the voltage drop
across R1, which is less than V.
u The equation and comments above assume that no current flows
through the output terminal (i.e., the gate is connected to something
with infinite input resistance).
o Exercise: Plot the output voltage Eout against time as

the switch position is changed. o The actual time required to change the output voltage
is determined by the RC time constant of the charging
circuit. If Ror C is 0, it can change instantaneously; if
R or C is > 0 the switching time is greater than zero.
n As a result of the resistance and capacitance inherent in all
real gates, the output voltage of real and ideal gates are as
given below.
Eout
7
3.6. Timing Parameters n All signals take time to change
u tTLH = trise = Time to make a low-to-high transition
o Gate Timing Parameters u tTHL = tfall = Time to make a high-to-low transitionGate
n The propagation delay of a gate is the time required for an input signal time
change to produce an output signal change VH VL+.9(VH-VL)
n The propagation delay usually depends on whether the VL
VL+.1(VH-VL)
output signal transition is high-to-low or low-to-high tTLH tTHL
u tP - Propagation delay (worst case)
u Gate delays vary with
u tPHL - High-to-Low propagation delay
u tPLH - Low-to-High propagation delay
n The gate manufacturer only specifies a worst case value for

delays, and guarantees it will never be worse, if the gate is
operated in specified ranges
o Data sheet delay values o Timing Diagrams

n Data sheets give the propagation delay between input and output
terminals n We use timing diagrams to show how signals vary with
n In most cases they give both tpLH and tpLH. Remember these are changes time
at the output terminal. u The signal value (usually voltage) is plotted on the vertical axis and
n The data sheet always gives the maximum delay. time on the horizontal axis.
n They also frequently give a typical delay, which is useless u Data sheets also frequently use timing diagrams to specify exactly
what they mean be the timing parameters
n Listing a minimum delay would be useful, but it not usually given (it is
given for some of the newer high speed logic families). n Single signals (i.e., the signal on a single wire)
n If the minimum delay is not given and you need it, the safest
assumption is to assume it is zero. You could also estimate it to be B
between 1/4 and 1/3 the typical delay. 1 P
B Y P
u There are some sequential circuits that will not work if the delay is actually zero.
1 tBP tBP
n Minimum and maximum delays are worst cases figures X
u Data sheets give the range of conditions (e.g., temperature, capacitive load, etc.) for X
which the delay values are guaranteed. tBX tBX
max t BYLH = max tNANDHL + max tNANDLH
u Sometimes these are given by means of graphs.
min t BYLH = min tNANDHL + min tNANDLH Y
tBY tBY
8
u Delay variations 3.7. Voltage Parameters, Noise Margins and Fan-In
o Voltage Parameters
B n Inverter Transfer Characteristics
Y
VOH = minimum high state
min tP
max tP output voltage
VOL = maximum low state
output voltage
n Multiple signals (i.e., a bus)
VIH = minimum high state
input voltage
VIL = maximum low state
Stable Stable Stable input voltage
Stable Stable Stable
Stable Stable
n Note that VOH > VIH and VOL < VIL. Why?
o Noise Margins o Fan-In: the number of inputs on a gate

vo vi VDD
RL
vi = vo + vn, where vn is noise
Vo
n Noise margin is a measure of how much noise a gate can Vi1
safely tolerate.
Vi2
Vmax
NMH VOH
VIH
Vik
NML VIL
VOL
Vmin Vo = kRN / (RL + kRN) Vo = (RN/k) / (RL + (RN/k))
NMH = VOH - VIH
NML = VIL - VOL n What effect does fan-in have on noise margin for these two gates?
9
3.8. Current Parameters and Fan-Out
o Fan-Out: The maximum number of gates of a given
type that can be driven by one gate of a possibly
different type.
n Each gate input draws current from whatever is driving it
n When a gate drives more than one gate input terminal, the
total current the driving gate must supply is a function of
number of gates it drives.
n There is a maximum amount of current that a given gate
can supply from its output terminal.
n Therefore, there is a limit on the number of gate input
terminals that you can connect to one gates output terminal
(i.e., the fan-out of the driving gate).
n This section shows how to calculate the fan-out of gates.
n Which gate has better noise margins?
o Current Parameters n If current flows into a gate output terminal, that gate is said
n The load seen at a gate output terminal is the current it to sink current.
must source or sink to drive other gate input terminals. n If current flows out of a gate output terminal, that gate is
n IIL - Maximum input current at a gate input terminal with said to source current.
its input voltage low
n IIH - Maximum input current at a gate input terminal with i
Driven
its input voltage high Driving
Gate Gate
n The amount of current flowing through a gate's output Sourcing Current
terminal (output load) is determined by the number of gate
input terminals it is connected to
i
u If a gate output is connected to n gate inputs, the load on the Driving Driven
driving gate can be as high as nIIL in the low state and nIIH in the Gate Gate
high state, but it will not be higher Sinking Current
10
o Fanout Calculations n Example #2
n The sum of the maximum input currents of the driven gates 0.03Æ 1
2¨
must be less than the maximum possible output current of 0.03Æ
2
the driving gate, in both the high and low states 1.0Æ 2¨
15¨
0.03Æ
n Example #1 Sourcing Analysis: 2¨
n
n Example #3 (Mixed gate types)

0.05Æ
2¨
1
0.05Æ
2
0.5Æ 2¨ Sinking Analysis: 0.04 Æ
1.6 ¨
20¨
0.04 Æ
0.05Æ n 1.6 ¨
2¨ 0.4 Æ 0.02 Æ
8.0 ¨ 0.4 ¨
0.02 Æ
0.4 ¨
Fanout = 0.02 Æ
o Fan-Out in CMOS Circuits 3.9. Special Gate Circuits

n While the fan-out of CMOS gates is affected by current o This sections introduces several special types of gate
limits as shown in the previous section, the fan-out of circuits developed for specialized situations. These
CMOS gates driving CMOS gates is enormous since the
input currents of CMOS gates is very low. include:
u Why are the input currents low? n Transmission gates
n On the other hand the high capacitance of CMOS gate n Tri-State output circuits
inputs means that the capacitive load on a gate driving n Open Collector output circuits
CMOS gates increases with fan-out. n Schmidt trigger input circuits
u This increased capacitance limits switching speeds and is a far
more significant limit on the maximum fan-out.
V o for n =1
VDD
V o for n = 4
Gnd Time
0
11
o Transmission Gates
n Passing 0s and 1s through an MOS Transistor
u N-Channel MOS Transistors pass a 0 better than a 1
n A transmission gate is a essentially a switch that connects
VDD VDD two points. In order to pass 0’s and 1’s equally well, a pair
of transistors (one N-Channel and one P-Channel) are used
GND v = GND VDD v <VDD
as shown below:
Passing 0 Passing 1 s
s
u P-Channel MOS Transistors pass a 1 better than a 0
x y x y
VDD VDD s
s Symbol
GND v> GND VDD v =VDD
Passing 0 Passing 1
Circuit
u When s = 1 the two transistors conduct and connect x and y
u This is the reason that N-Channel transistors are used in the pull-down
l The top transistor passes x when it is 1 and the bottom transistor passes x
network and P-Channel in the pull-up network of a CMOS gate. Otherwise when it is 0
the noise margin would be significantly reduced.
u When s = 0 the two transistor are cut off disconnecting x and y
n Implementing XOR gates n Implementing a multiplexer with transmission gates

u With NAND gates and inverters:
X1
x
S Y = X1•S+X2•S
x⊕y X2
y
u With transmission gates u When S = 0, input X1 is connected to the output Y
u When S = 1, input X2 is connected to the output Y
x
y
x⊕y
u Why would one of these circuits be preferable to the other?
12
o Tri-State Outputs
n The switch on the output could be implemented by a
n Instead of the usual two, these outputs have three possible
transmission gate
states, 0, 1, and Z (high impedance) C
u States 0 and 1 are standard logic levels
u State Z is called the high impedance output state. It is not a logic Gate
level.
u Is the control signal C asserted high or low? How would you

change the circuit to assert it the other way?
n Three-State buffers are the preferred way to implement

n A tri-state gate is realized by adding a switch to the output buses.
of a regular gate. This switch is controlled by an external
output control signal.
u When the output control signal is asserted, the switch is closed and
the gate acts like a normal gate.
u When the output control signal is deasserted, the switch is open and
the gate is disconnected from its output terminal.
o Verilog description of n-bit tri-state module o Open-Output circuits (Open Collector or Open Drain)
module trin (Y, E, F); n Connecting passive pull-up outputs together
parameter n = 8;
input [n-1:0] Y;
input E;
output [n-1:0] F;
wire [n-1:0] F;
assign F = E ? Y : 'bz; X X Z
Z
Y Y
endmodule
Logically equivalent logic diagram Wired AND Logical Symbol
n The conditional statement F = E ? U : 'bZ; is the same as
if (E) F = U; else F = ‘bz; u Advantage: free AND gate
n Note that ‘bz is an unsized number that is expanded to the u Disadvantage: reduces pullup resistance and increases power
length of the left side of the assignment statement. dissipation
13
n Solution to problem of reduced pullup resistance: move n Examples of wired AND logic
pullup from inside to outside the gate so designer has
control of its value
n Examples of Open-Output gates
Z
Z
X
X
Y
u To use these gates, the designer MUST add an external pull-up

resistor
n Open-Output Symbol
o Schmitt Trigger Inputs n Ideal Gate

n Standard gate
14
3.10. Tips & Tricks
n Gate With Schmitt Trigger Input o The pullup network can be derived from the pulldown
network by swapping series connections with parallel
connections.
o Use speed vs. capacitive load to calculate fan-out in
CMOS circuits
o Use Schmidt trigger gates as bus recievers and tri-
state gates as bus drivers.
o Tying together gate outputs unless they are designed

to support it.
3.11. Pitfalls 3.12. Review

o Not designing the pullup and pulldown networks of
active pullup gates to be exact complements of one o The use of switches to realize logical operations.
another. o The relationship between pull-up and pull-down
o Using typical values of gate parameters instead of networks used in gate implementations.
minimum and maximum gate parameters. o The structure of MOSFET transistors.
o Activating multiple bus drivers on the same bus wire. o The differences between ideal and real switches.
o The effect of resistance and capacitance on switching
speed.
o The effect of resistance on fan-out and fan-in.
o The implementation and use of tri-state outputs, open-collector
outputs, and Schmidt trigger inputs.
15

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3.

Physical Properties of Gates

3.1. A Structural Model for Gates

terminals just in case both the signals X and Y are 1.

Y Passive Pullup Active Pullup

Passive Pullup Active Pullup

n NOR Gates n General Model

u For the NOR gate T connects iff either X or Y is 1.

3.2. MOSFET Transistors

u The ideal normally closed switches presented in Section 4.1 are

3.4. TTL Logic Families

between the gate and substrate vi

Series Delay Power Speed-Power

74Lxx 33ns 1mW 33pJ pin 1 pin 14

3.5. Differences Between Real and Ideal Gates

1 VCC 14 1 VCC 14 1 VCC 14 1 VCC 14

o Exercise: Plot the output voltage Eout against time as

n The gate manufacturer only specifies a worst case value for

o Data sheet delay values o Timing Diagrams

o Noise Margins o Fan-In: the number of inputs on a gate

n Example #3 (Mixed gate types)

o Fan-Out in CMOS Circuits 3.9. Special Gate Circuits

n Implementing XOR gates n Implementing a multiplexer with transmission gates

u Why would one of these circuits be preferable to the other?

u Is the control signal C asserted high or low? How would you

n Three-State buffers are the preferred way to implement

u To use these gates, the designer MUST add an external pull-up

o Schmitt Trigger Inputs n Ideal Gate

o Tying together gate outputs unless they are designed

3.11. Pitfalls 3.12. Review

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